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| PRELIMINARY DATA SHEET MICRONAS MAS 35xyH Audio Decoder IC Family SURROUND P R O L O G I C II SPATIALIZER N-2-2 ULTRATM DIGITAL Edition Dec. 4, 2003 6251-589-2PD MICRONAS MAS 35xyH Contents Page 5 5 6 7 9 9 9 9 10 10 10 11 11 11 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 14 15 15 15 15 16 16 16 16 18 18 18 18 18 18 19 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.7.1. 2.7.2. 2.7.3. 2.7.4. 2.7.4.1. 2.7.5. 2.8. 2.9. 2.9.1. 2.9.2. 2.9.3. 2.9.4. 2.9.5. 2.9.6. 2.9.7. 2.9.8. 2.9.9. 2.9.10. 2.9.10.1. 2.9.10.2. 2.9.11. 2.9.12. 2.9.13. 2.9.14. 2.9.14.1. 2.9.14.2. 2.9.14.3. 2.9.15. 2.9.16. 2.9.17. 2.10. 2.10.1. 2.10.2. 2.10.3. Title Introduction Features TV System Application TV Application Details Functional Description Overview Architecture DSP Core Internal Program ROM and Firmware RAM and Registers Clock Management Interfaces I2C Control Interface S/PDIF Input Interfaces S/PDIF Output Serial Input Interface Multiline Serial Output Frame Synchronization Power-Supply Regions Functional Blocks and Operation Power-Up Sequence and Default Operation Input Switching Standard Selection and Decoding Dolby Digital Data Stream DTS (Digital Theater Systems) Data Stream MPEG Layer-2 Data Stream PCM Audio Data De-emphasis Dolby Pro Logic II Input Matrix Dolby Pro Logic II Decoder Major Operational Modes of Pro Logic II Additional Operational Modes Channel Expander Noise Generator Virtual Dolby Digital Post Processing/Bass Management Extra Stereo Output Digital Volume Bass Management Output Format Selection S/PDIF Loop-Through Output Sampling Rate System Interaction Minimum Required Interconnections Required Special Modes in the System Minimum System Set-Up PRELIMINARY DATA SHEET 2 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Contents, continued Page 20 20 20 20 20 20 21 21 21 23 23 23 23 24 24 24 25 27 27 38 49 51 51 53 56 56 56 56 56 56 56 56 56 56 57 59 60 60 61 61 62 62 62 63 64 65 Section 3. 3.1. 3.2. 3.2.1. 3.2.2. 3.2.3. 3.2.4. 3.3. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. 3.4.5. 3.4.6. 3.4.7. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.3.7. 4.3.8. 4.3.9. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. Title Control Interface Start-Up Sequence I2C Interface Access General I2C Registers and Subaddresses Conventions for the Command Description The Internal Fixed Point Number Format I2C Control Register (Code 6Ahex) I2C Data Register (Codes 68hex and 69hex) and the MAS 35xyH DSP-Command Syntax Read Register (Code Ahex) Write Register (Code Bhex) Read Memory (Codes Chex and Dhex) Short Read Memory (Codes C4hex and D4hex) Write Memory (Codes Ehex and Fhex) Short Write Memory (Codes E4hex and F4hex) Default Read Registers Special Memory Locations and User Interface Status Interface for Decoding Control Interface for Decoding Operation Hybrid User Interface Cells Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Control Lines General Purpose Input/Output Clocking Serial Input Interface S/PDIF Input Interface S/PDIF Output Interface Serial Output Interface Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Reference Frequency Generation and Crystal Recommendations Characteristics General Characteristics I2C Characteristics S/PDIF Bus Input Characteristics S/PDIF Bus Output Characteristics Micronas Dec. 4, 2003; 6251-598-2PD 3 MAS 35xyH Contents, continued Page 66 67 68 69 72 Section 4.6.3.5. 4.6.3.6. 4.6.4. 5. 6. Title I2S Bus Characteristics - Input I2S Characteristics - Output Firmware Characteristics Application Data Sheet History PRELIMINARY DATA SHEET License Notice: DTS, DTS Digital Surround, and DTS Virtual 5.1 are trademarks and the "DTS" Logos are registered trademarks of the Digital Theatre Systems Corporation. "Dolby Digital", "Pro Logic ", and the double-D Symbol are trademarks of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-touse final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products. Spatializer(R), Spatializer N-2-2`, and the circle-in-square device are trademarks of Desper Products, Inc. 4 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH In a consumer audio application, the MAS 35xyH, completed by a standard audio codec and power amplifiers, forms a 5.1 multichannel audio A/V amplifier or receiver. The high integration level of MAS 35xyH with its S/PDIF on chip, enables the design of very economic 5.1 home audio sets. Audio Decoder IC Family This data sheet applies to the MAS 35xyH family, version C6, and to following versions. Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The Micronas MAS 35xyH family consists of ICs with various combinations of DTS, Dolby Digital, Dolby Pro Logic II and MPEG-1 Layer-2 decoders and Virtualizer on a single chip. The family consists by the following members: Table 1-1: MAS 35xyH family Decoder 3527H DTS Dolby Digital Pro Logic II VDD (Virtual Dolby Digital) VDS (Virtual Dolby Surround) MPEG1 L2 N-2-2 ULTRA - - - optional MAS35xyH Type 3529H - optional 3530H optional 1.1. Features - Two multiplexed S/PDIF, IEC-958, IEC 61937, AES/ EBU, EIA-J CP-340 receivers - Two freely configurable multiplexed serial inputs - Decoders for 5.1 Dolby Digital (AC-3), 5.1 DTS, Dolby Pro Logic II and MPEG-1 Layer-2 - Spatializer N-2-2 ULTRA as "Virtual Dolby Digital"compliant virtualizer - Handling of PCM input format - S/PDIF PCM output or loop-through for all inputs - Lt, Rt encoding or straight downmixing to two channels (Lo, Ro) simultaneously to 5.1 multichannel output - Multichannel I2S output (four stereo data lines or one 8-channel line) - Dynamic range compression - Karaoke downmixing - Delay for center (0...5 ms) - Delay for surround (two channels, 0...25 ms) - Bandpass-shaped/white-noise generator - Bass management according to Dolby specification (output configuration 0, 1, 2, 3, and DVD) and "Bass to Center" - I2C control The MAS 35xyH decoder IC acts as a complete implementation of 5.1 DTS and Dolby Digital/Pro Logic II decoders. On the chip's 8-channel output an Lt/Rt or Lo/Ro downmix is available simultaneously to the multichannel audio for recording or headphone usage. All necessary processing units, together with the I/O interfaces, have been integrated in a single 44-pin IC. In a TV application, a two-chip solution of MAS 3527H and MSP 44x0G results in a Virtual Dolby Digital System, whereas a multichannel audio TV uses MAS 35xyH, MSP 44x0G and DPL 4519G. Due to the scalable and flexible Micronas system solution, a single hardware (PCB) solution, as well as a single TV software solution, can be used to implement TV audio systems from stereo only, via Virtual Dolby Digital, to DTS/Dolby Digital multichannel audio. Micronas Dec. 4, 2003; 6251-598-2PD 5 MAS 35xyH 1.2. TV System Application The Micronas DTS/Dolby Digital TV system solution consists of three dedicated integrated circuits: - The MSP 44x0G is the interface for all TV-sound and analog input signals. It performs the TV-audio demodulation and stereo decoding. It has four pairs of audio D/A-converters, two of them including sound control facilities, and one additional subwoofer D/A converter. - The DPL 4519G adds three pairs of audio D/A-converters, two of them including sound control facilities, and one additional subwoofer D/A converter. - The MAS 35xyH performs DTS/Dolby Digital or MPEG decoding, Pro Logic II decoding for all Stereo Sources, Virtual Dolby Digital processing for surround sound with 2 speakers. PRELIMINARY DATA SHEET DVD S/PDIF DVB PCM / Dolby Digital MPEG via I2S Serial S/PDIF out MAS 35xyH I2S/Serial I 2S 8 ch L/(Sub)/R or L/(C)/R DPL 4519G I 2S 2 ch I2S SCART 8 ch SL/SR L/(Sub)/R or L/C/R or C/C TV SIF Tuner MSP 44x0G 1...8 ch VCR SCART (TV+Stereo) SCART Fig. 1-1: Configuration of the Micronas DTS Dolby Digital/TV system solution. Lt/Rt or Lo/Ro 6 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 1.3. TV Application Details SPDI1 Deemphasis SPDIF In 1/2 SPDI2 Input Buffer SID* SII* SIC* PCM Virtualizer N-2-2 Post Processing Delay Lines ProLogic II MPEG L R Ls Rs C/ Sub Lt Rt SPDO 2 SPDIF Out AC-3 SOD3 SOD2 SOD1 SOD SOI SOC Multipl. I2S-In: Slave SID SII SIC DTS Noise Gen. 'Signal mapping configurations Example 1: - internal L,C,R - internal woofer for low freq. of L,(C),R - ext.Surroundspeakers SL,SR - ext.Subwoofer for SUB Channel. Exanple 2: - internal Left and Right used as C - internal woofer for low freq. of C - ext.L,R - ext.Surroundspeakers SL,SR - ext.Subwoofer for SUB Channel. Configuration Examples 18.432 MHz Amp./ Osc. PLL Synth. MAS 35xy H CLKO I2S-Multichannel Mode (6 - 8 Channels, fs=32, 44.1 or 48 kHz, 16,18,....32 Bit) 4 I2S_1_L I2S_1_R I2S_2_L I2S_2_R I2S_3_Lt 2-8 Channel async. Input L T , RT , L, R SL, SR, C, SUB I2S_3_Rt L R SL SR C SUB 8 channels stereo Dolby Digital / DTS / ProLogic II 1 2 Lext SUBext Rext SL SR I2S_Inputs 1 I2S_WS3 I2S_CL3 2 3 Bass Treble Balance Volume Bass Treble Balance Volume Speaker D/A analog Volume D/A analog Volume Headphone ----SCART1 SL SR ------Cint SUBext (Cint) AUDIO_ CL_OUT 18.432 MHz Volume D/A I2S_Out_L/R ----- Lt Rt L, R C, SUB SL, SR Lt, Rt Lt Rt L, R C, SUB SL, SR Lt, Rt --- I2S_WS I2S_CL Upgrade Module Basic TVSound System DPL 4519 G Lt, Rt, L, R, SL, SR, C, SUB I2S_Inputs 1 I2S_WS3 I2S_CL3 I2S_WS I2S_CL 2 3 4 I2S_1_L I2S_1_R I2S_2_L I2S_2_R I2S_3_Lt I2S_3_Rt I2S_3_L I2S_3_R I2S_3_SL I2S_3_SR I2S_3_C I2S_3_SUB SoundProcess. Balance Volume Bass Treble Balance Volume Volume D/A analog Volume D/A analog Volume Speaker L Subw R Lint Subwint Rint Cint Subwint Cint Headphone 18.432 MHz L R L R L R Lt Rt Lt Rt Lt Rt Lt Rt Lt Rt Lt Rt 2-8 Channel sync. Input SCART1 D/A SCART2 Volume D/A SIF-IN SCART1_In 2 . . . Demod I2S_Out_L/R L, R L, R L, R A/D MSP 4450 G Multistandard Sound Processor SCART4_In Fig. 1-2: Block diagram of the MAS 35xyH TV application with output signal mapping Micronas Dec. 4, 2003; 6251-598-2PD 7 MAS 35xyH PRELIMINARY DATA SHEET GPIO S/PDIF MAS 35xyH S/PDIF out I2S Line in (analog) I 2S 6 x Power Amplifier Volume L C R Sub SL SR L C R Audio Codec A/D and D/A Line out (analog) Fig. 1-3: Block diagram of an MAS 35xyH 5-1 Multichannel Audio Amplifier/Receiver application 8 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 2.2. Architecture The hardware of the MAS 35xyH consists of a high performance RISC Digital Signal Processor (DSP) and appropriate interfaces. Fig. 2-1 shows a hardware overview of the IC; Fig. 2-2 on page 12 shows the functional aspects. 2. Functional Description 2.1. Overview The MAS 35xyH is intended for use in consumer audio applications. It receives S/PDIF or serial data streams and decodes the DTS Dolby Digital (AC-3), MPEG or PCM-encoded audio formats. Due to the automatic format detection, no controller interaction is needed for the standard operation. On the other hand, the controller has full access to all vital information contained in the Dolby Digital or DTS bit stream. The choice of different output formats, as defined by Dolby, guarantees a good adaption to various listening environments. 2.3. DSP Core The internal processor is a dedicated audio DSP. All data input and output actions are based on a `noncycle-stealing' background DMA that does not cause any computational overhead. MAS 35xyH DSP-Core MAC ALU PIO Interface GPIO 1 S/PDIF 2 1 Serial Audio (I2S) 2 S/PDIF Input Interface Accumulators S/PDIF Output Interface S/PDIF ROM Serial Input Interface SOD D0-RAM D1-RAM SOD1 SOD2 I2C-Bus to controller IC Slave Interface 2 I2S Serial Audio Additional I2S data lines CLKO 9 Registers SOD3 Processor Clock 18.432 MHz XTI XTO Quartz Osc./ Clock Input System Clock Synthesizer Divider Reference Clock Divider Fig. 2-1: The MAS 35xyH architecture Micronas Dec. 4, 2003; 6251-598-2PD MAS 35xyH 2.4. Internal Program ROM and Firmware The firmware implemented in the program ROM of the MAS 35xyH provides Dolby Digital, DTS and MPEG-1 Layer-2 audio data decompression as well as handling of PCM-encoded audio. All Stereo sources (PCM, MPEG1L2, DD 2/0, DTS 2/0) pass through a Dolby Pro Logic II decoder. The required downmixing, output configurations and delay lines for an implementation of Dolby Digital or DTS and loop-through of unsupported formats received via the S/PDIF input are implemented as well. For PCM and MPEG signals, a de-emphasis can be applied to achieve a flat frequency response. On power-on, the DSP starts the firmware in an automatic standard detection mode with the first S/PDIF input selected. Therefore, only minimal controlling is necessary. In addition, the I2C interface provides a set of I2C instructions that give access to internal DSP registers and memory areas. PRELIMINARY DATA SHEET 2.6. Clock Management The MAS 35xyH is driven by a single clock at a frequency of 18.432 MHz. The clock may either be provided by an external source connected to pin XTO, or by a crystal connected to XTI and XTO. In this case, the clock signal is available for other applications at pin XTO. The internal reference clock and processor clock are derived from the 18.432 MHz and synchronized to the audio sample frequency of the decompressed bit stream by a PLL. For Dolby Digital decoding, the clock frequency can be selected as a high or a low value in configuration memory cell UIC_Out_Clk_Scale (D0:13DF) by bit[16] - (see Table 3-8 on page 49). It is highly recommended to use the high system clock. The resulting processor clocks are given in Table 2-1. At pin CLKO, a clock output can be provided, e.g., for additional D/A converters. The output frequency at CLKO is the reference clock divided by a factor as selected by bits [18:17] in D0:13DF. By default, CLKO is disabled. Table 2-1: Processor clock frequencies and reference clock frequencies in dependence of bit [16] of UIC_Out_Clk_Scale (D0:13DF) Format fs/kHz Processor Clock/MHz bit[16] = 0 Dolby Digital, DTS, MPEG, PCM 48 44.1 32 61.44 56.448 40.96 bit[16] = 1 73.728 67.7376 49.152 2.5. RAM and Registers The DSP core has access to two RAM banks named D0 and D1. All RAM addresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For more details, please refer to Section 3.4.on page 21. For fast access of internal DSP states, the processor core has an address space of 256 data registers (see Section 3.5. on page 25) which can be accessed via I2C bus. 10 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 2.7.4. Serial Input Interface If the serial input interface carries Dolby Digital, MPEG Layer-2, or PCM, the MAS 35xyH processes the data. The interface consists of the three pins: SIC, SII, and SID. For MPEG and Dolby Digital decoding operation, the SII pin must always be connected to VSS, while for PCM data, the interface acts as an I2S type and SII is used as a word strobe. An example of an input signal format is shown in Fig. 4-18 on page 66. The data values are latched with the falling edge of the SIC signal. It is possible to use a word length of 16 or 32 bits. For controlling details, please refer to memory address D0:13D0 (I/O Control) and D0:13DF (Auxiliary Interface Control) in Table 3-7 on page 38. If the MPEG or Dolby Digital signal was formatted (e.g. to 8-bit or 16-bit words) by the storing or transportation medium (PC, memory), the serial data has to be sent "MSB first" as produced by the encoder. 2.7. Interfaces 2.7.1. I2C Control Interface For controlling, a standard I2C interface is implemented. A detailed description of all functions can be found in Section 3. on page 20. 2.7.2. S/PDIF Input Interfaces Two multiplexed S/PDIF input interfaces are installed which are capable of PCM, Dolby Digital, DTS and MPEG auto-detection. In addition to the signal input pins SPDI/SPDI2, a reference pin SPREF is provided to support balanced signal sources or twisted pair transmission lines. The following features are supported: - Fast synchronization on input signal (< 50 ms) - Burst Mode support for Dolby Digital, DTS and MPEG bit streams - Locking on 32, 44.1, 48 kHz sample frequencies - Incoming first 20 channel status bits are mirrored in Register 56hex (see Table 3-5 on page 25) When the input format is changed (e.g. from Dolby Digital to MPEG), the synchronization is lost and the audio output is muted. The automatic standard recognition then checks the new input format and, after successful recognition, resumes normal operation. It is possible to observe the S/PDIF input for valid bitstreams while processing IS signals, (see Table 3-6), Adr. D0:13C7hex. Detection whether the interface has synchronized or not, and what the S/PDIF header information contains, is possible. This permits the following implementations: - automatic detection whether signals are connected to the digital input or not, during normal operation mode ("hot plug-in") - automatic fallback to analog sources when undecodable bit streams are detected, with automatic switchback when the signals are decodable again. 2.7.4.1. Multiline Serial Output The serial audio output interface of the MAS 35xyH is a standard I2S-like interface consisting of four data lines SODx, the word strobe SOI, and the clock signal SOC. The output bit stream can either carry eight channels on one line (SOD) or two channels on each of four lines (SOD, SOD1, SOD2, SOD3). Further, it is possible to choose between different interface configurations (with word strobe time offset and/or with inverted SOI signal) and to tristate the output interface. The serial output generates 32 bits per audio sample, but only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default (see Fig. 4-20 on page 67). The configuration of the output interface is done in D0:13D0 and D0:13DF (see Table 3-7 on page 38). 2.7.5. Frame Synchronization For microprocessor interrupts, a frame synchronization output pin (SYNC) is provided. After decoding a valid header, the SYNC pin level changes to High. Most of the status information (UIS cells in Table 3-6 on page 27) is updated now. To generate an edge for the controller, the level changes to Low during processing the next header. After having completed this, the SYNC pin level changes to High again. If the level is Low for more than 1 ms, no decoding is performed. Memory cell UIH_LAST_MESSAGE (D0:13FF) provides background information thereon. 2.7.3. S/PDIF Output At pin SPDIFOUT, the baseband audio is provided as an S/PDIF signal. Channel status bits in S/PDIF output (especially copyright, category code and generation status) can be configured in D0:13EA (see Table 3-7 on page 38). Alternatively, this output can mirror the unprocessed signal of the S/PDIF input (Output_Conf: Register 2Ehex). This loop-through is necessary for signals where no internal decoding action is performed. Micronas Dec. 4, 2003; 6251-598-2PD 11 MAS 35xyH Notes for Dolby Digital: After first CRC is done, the SYNC pin level changes to High, all information for a frame is valid, and decoding is performed. The SYNC pin level changes to Low before new status information is written. Please take into account that UIS_DYNRNG (D0:13B4), UIS_DYNRNG2 (D0:13B5), and UIS_KARAOKEFLAG (D0:13B6) are valid for the audio block only; the SYNC pin does not signalize their validity. PRELIMINARY DATA SHEET 2.9. Functional Blocks and Operation For a block diagram of the MAS 35xyH functionality please see Fig. 2-2. 2.9.1. Power-Up Sequence and Default Operation After applying the appropriate voltages to the three supply pins and releasing the reset signal, the circuit starts normal operation with S/PDIF (SPDI) as the expected input and automatic standard recognition (Dolby Digital, DTS, MPEG, PCM). No further action is necessary for default operation or loop-through of undecodable data streams. A power-on reset can be issued at any time via pin POR. Notes for MPEG: After processing CRC, the SYNC pin level changes to High, all information for a frame is valid, and decoding is performed. The SYNC pin level changes to Low before evaluating new header information. 2.8. Power-Supply Regions The MAS 35xyH has three power supply regions. The VDD/VSS pin pair supplies all digital parts including the DSP core. The XVDD/XVSS pin pair is connected to the signal pin output buffers. The AVDD/AVSS supply is for the clock oscillator, PLL circuits, and system clock synthesizer. 2.9.2. Input Switching Both input interfaces, the S/PDIF or the serial input interface, may carry any of the three data formats: Dolby Digital (AC-3), MPEG Layer-2, or PCM. The S/PDIF input may carry DTS data as well. The filling status of the input buffer represents the data rate and therefore controls the system clock. The input interface can be selected in the UIC_IO control D0:13D0. MAS 35xyH Deemphasis PCM 2 ProLogic II Decoder Output Buffers 5 2 2 Virtual Dolby Digital and Downmix Multiplexer 2 8 Serial Inputs Input Buffer S/PDIF Inputs MPEG1L2 2 Decoder 2/0 Lt/Lo Rt/Ro Bass Management Volume and Delay L R LS RS C SUB 6 SOD SOD1 LtRtLoRo Down mix 2 2 AC-3 Decoder 1+1,1/0, 3/0, 2/1, 3/1, 2/2, 3/2 LFE 5 2 5 2 SOD2 SOD3 S/PDIF Output 2/0 2 DTS Decoder Buffer Fill Information 1/0, 3/0, 2/1 3/1, 2/2, 3/2 LFE Noise Gen. Processor Clock Clock/ Crystal Amp./ Oscill. 18.432 MHz 2 div PLL Synthesizer div Reference Clock CLKO Note: No. of Channels (e.g. 2): Fig. 2-2: Functionality of the Audio Decoder IC Family MAS 35xyH 12 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 2.9.5. DTS (Digital Theater Systems) Data Stream The digital input signal must be an S/PDIF source. In DTS mode, the IC performs: - Data input with clock synchronization - S/PDIF channel selection (one of eight possible) - Decoding of DTS bitstream - Output mode control 2.9.3. Standard Selection and Decoding In the default mode, an automatic standard recognition (auto-detection) selects the decoding algorithm according to the data format at the S/PDIF input. The detected standard is shown in the Global Operating Status (D0:13BB). The standard selection for the I2S inputs can be selected manually in the I/O control D0:13D0. If the input contains only a stereo pair (PCM, MPEG, DD2/0, DTS2/0), it is automatically fed into the ProLogic II decoder, which generates a 5-channel output by default. The ProLogic II decoder may be deactivated by means of UIC_DPL_STANDARD (D0:13EE). - Bass Management according to Dolby specification - Center and surround delays The controller can select one of eight content channels depending on availability (D0:13BC). The respective service information is displayed in cell Bit Stream Mode (D0:13A2). The bit stream elements contain all necessary information required to correctly handle the audio. All elements important for controller actions are displayed in the status memory (see Table 3-6 on page 27). The MAS 35xyH decodes all DTS formats from 1 to 5.1 audio channels. Accordingly, one to six of the output channels are used for the decoded audio. The output mode is selected in D0:13D6. An additional downmix pair can either be Dolby-Surround-encoded (Lt, Rt), or plain stereo (Lo, Ro; D0:13DE). 2.9.4. Dolby Digital Data Stream The digital input signal can either be an S/PDIF or an I2S source. In the Dolby Digital mode, the IC performs the following tasks: - Data input with clock synchronization - S/PDIF channel selection (one of eight possible) - Decoding of AC-3 bit stream elements - Compression control for Dolby Digital signals (D0:13D7...13D9) - Output mode control - Dolby Bass Management - Center and surround delays - Level adaption If the signal source is the S/PDIF input, the controller can select one of eight content channels depending on availability (D0:13BC). The respective service information is displayed in cell Bit Stream Mode (D0:13A2). The bit stream elements contain all necessary information required to correctly handle the audio. All elements important for controller actions are displayed in the status memory (see Table 3-6 on page 27). The MAS 35xyH decodes all Dolby Digital formats from 1 to 5.1 audio channels. Accordingly, one to six of the output channels are used for the decoded audio. The output mode is selected in D0:13D6. An additional downmix pair can either be Dolby Surround encoded (Lt, Rt) or plain stereo (Lo, Ro; D0:13DE). 2.9.6. MPEG Layer-2 Data Stream In the MPEG mode a valid MPEG-1 Layer-2 data signal is expected. The steps for decoding are - Clock synchronization to data input - S/PDIF channel selection (one of eight possible) - Side information extraction - Audio data decompression - Optional de-emphasis - Digital volume If the signal source is the S/PDIF input, the controller can select one of eight content channels depending on availability (D0:13BC). Micronas Dec. 4, 2003; 6251-598-2PD 13 MAS 35xyH 2.9.7. PCM Audio Data PCM data can be received via S/PDIF or I2S. When received via S/PDIF, the sampling frequency will be detected automatically and mirrored in D0:13A0 (UIS_FS_CODE). If the PCM data are received via I2S bus, the MAS 35xyH expects a valid word strobe, and I/O control (D0:13D0) has to be set as described in Table 3-7. In this case the de-emphasis must be activated by the controller if necessary. PRELIMINARY DATA SHEET 2.9.10.1. Major Operational Modes of Pro Logic II Movie Mode The Movie mode in Pro Logic II is very similar to that of the original Pro Logic decoder. The main difference is that it has stereo surround channels and no surround filter, unlike Pro Logic which has a mono surround channel and a 7 kHz surround filter. Movie mode is the standard required for all A/V systems. When an autosound unit has a video screen, it is also considered as an A/V system. It can simply be called "Pro Logic II." Music Mode The Music mode offers the users some flexibility to control the results according to their own taste. Music mode should not be used with a THX audio processing mode. Music mode is recommended as the standard mode for auto-sound music systems (without video) and is optional for A/V systems. It is recommended that Music mode be identified as the "Music" version of Pro Logic II, to distinguish it from the Movie mode. Virtual Mode 2.9.8. De-emphasis For the PCM and MPEG formats, a de-emphasis can be applied to the signal (D0:13E0). This is necessary, as the possibly following Dolby Pro Logic decoding requires a flat audio frequency response. For MPEGencoded audio and PCM transmitted via S/PDIF, this block is activated automatically. For proper operation of PCM signals via I2S, the controller has to determine whether the PCM signals have been pre-emphasized or not. 2.9.9. Dolby Pro Logic II Input Matrix In front of the Pro Logic II processing a matrix is implemented. Normal operation is "Stereo or A/B" for 2 channel inputs, but it is also possible to select only Sound A or Sound B (Mono Sound on both channels). This feature is used for bilingual MPEG transmissions. The required setup must be done by the controller in D0:13EE. The Virtual mode is usually used when Pro Logic II is connected to a virtual process for speaker use. However, there might be some virtualizers for which this mode does not produce the intended result. For those virtualizers, Movie mode may give the best surround effect. Virtual mode is designed to be used with the virtual process developed by Dolby Laboratories. The Pro Logic II mode should only be called "Pro Logic II" so that the name "Virtual" can be reserved to describe the speaker virtualization process itself. 2.9.10. Dolby Pro Logic II Decoder Every stereo source is automatically routed through the Dolby Pro Logic II decoder. (DD2/0, DTS2/0, MPEG, PCM, I2S from MSP44x0G). The Pro Logic II decoder decodes the stereo signal into a five channel surround sound signal. Six predefined operational coefficient sets and one customizable set allow different decoder modes for different sound material (Movie, Music, Virtual compatible, Pro Logic Emulation, Matrix, Custom and Bypass Mode), as Dolby proposes in its "Licensee Information Manual: Dolby Pro Logic II, Section 2.2". A variety of options and the Dolby Bass Management are used to adopt the decoder to the used speaker configuration. The required setup must be done by the controller in D0:13ED and D0:13EE. Note: To be Virtual-Dolby-Surround-compliant, the correct Pro Logic II operational mode for the built-in virtualizer is Movie Mode (not Virtual Mode). Pro Logic Emulation Mode The Pro Logic Emulation mode offers users the same robust surround processing as the original Pro Logic, for those cases where the source content is not of optimum quality, or if there is a desire to hear the program more "as it used to be." When this mode is used, it is called Pro Logic, as before. There is no "Pro Logic I" mode. The Pro Logic emulation mode is optional. Dolby does not require PLII products to use the original Pro Logic decoding algorithm. However, if the DSP contains the original Pro Logic code, and if the product maker would like to use it, this is quite acceptable and even encouraged. A product must not offer both original Pro Logic and the Pro Logic emulation mode. 14 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Panorama Mode In the Music Mode, this control extends the front stereo image to include the surround speakers for an exciting "wraparound" effect with side-wall imaging. It is particularly effective for recordings which have strong left or right channel elements in the mix, as these are detected and accentuated by the Panorama process. According to the LIM for Pro Logic II, Panorama Mode must only be switched on in Music Mode. Matrix Mode The Matrix mode is the same as the Music mode except that the directional enhancement logic is turned off. It may be used to enhance mono signals by making them seem "larger." The Matrix mode may also find use in auto systems, where the fluctuations from poor FM stereo reception can otherwise cause disturbing surround signals from a logic decoder. The ultimate "cure" for poor FM stereo reception may be simply to force the audio to mono. Custom Mode All settings are user defined Off (Bypass Mode) Pro Logic Decoding is switched off. Lt to L; Rt to R; Sl,Sr and C muted. 2.9.11. Channel Expander The outputs of the PCM/MPEG decoders consist of two channels each; the output of the Dolby Digital/ DTS decoder may have any number between one and six (5.1) channels. To unify the output format between different modes, the audio is always mapped to six channels. 2.9.12. Noise Generator 2.9.10.2. Additional Operational Modes Surround Filter There are two surround filters available in Pro Logic II. One is the 7 kHz lowpass filter for use with Pro Logic emulation mode; the other is the shelf filter for use with Music and Matrix modes. This latter filter is a mild shelving filter that improves the naturalness of the sound in Music mode. Surround Coherence In the Movie mode, it is important that the surround speakers be in phase, so that movie sound effects panned to or across the surrounds will have optimal localization and imaging. This is achieved with the surround coherence function (Right Surround Channel Polarity can be inverted). Stereo music content, however, does not contain panned surround effects, so it benefits from a more spacious presentation of the ambient sounds by turning off the surround coherence function. Auto-Balance This operates in the same way as in all previous Pro Logic decoders to ensure that movie sound tracks decode optimally. Additional signal processing may be included if Pro Logic II is allowed to operate fully and without modification in name or function. In other words, any additional signal processing must include a bypass mode to defeat the processing. When any additional process works in conjunction with Pro Logic II, it must clearly be indicated that both processes are working together. A bandpass-shaped or white noise signal can be routed to any combination of the six main output channels. The required channel sequence must be done by the controller in D0:13D1. No noise signal is available at the Extra Stereo Output. 2.9.13. Virtual Dolby Digital In the MAS 35xyH, Spatializer N-2-2 ULTRA is implemented as a Dolby Digital approved virtualizer. It takes advantage of the most advanced digital sound processing techniques available and is designed to process DTS, Dolby Digital and Pro Logic II sound tracks. Using only two (L, R) or three (L, C, R) loudspeakers, N-2-2 ULTRA produces a realistic surround sound impression in a large listening area. In MAS 35xyH, the "TV" version (N-2-2 ULTRA TV) of N-2-2 ULTRA is available. It is an optimization for playback over television loudspeakers. N-2-2 ULTRA TV takes advantage of the pre-determined listening configuration inherent to TV sets and reduces the control effort (number of parameters) while maintaining the highest quality virtual surround sound effect. All MAS 35xyH are shipped without Spatializer N-2-2 ULTRA except otherwise ordered. When an N-2-2 ULTRA version of MAS 35xyH is ordered, it carries a special marking on the chip for identification. The N-2-2 ULTRA functionality must be enabled by writing a "license key" into MAS 35xyH. For information on how to obtain this license key from Micronas, please contact your Micronas sales representative. A license from Desper Products Inc. is required before a MAS 35xyH with Spatializer N-2-2 ULTRA can be purchased. Micronas Dec. 4, 2003; 6251-598-2PD 15 MAS 35xyH PRELIMINARY DATA SHEET 2.9.14.3. Bass Management Note: To be Virtual-Dolby-Surround-compliant, the correct Pro Logic II operational mode for the built-in virtualizer is Movie Mode (not Virtual Mode). Generally, not all of the five loudspeakers in a Dolby Digital system can reproduce the full audio bandwidth. Bass Management allows redirecting low frequencies to loudspeakers which are capable of reproducing this frequency range. The MAS 35xyH supports the following Bass Management modes: Bass Management mode 0 (D0:13DA = 8) Attenuation of -15 dB in the SUB channel should be compensated by a 15 dB gain in the D/A-converter. L C R LS RS -15 dB x 5 2.9.14. Post Processing/Bass Management The implemented post-processing functions can be applied to the following audio formats. They are - Downmixing to Lo/Ro or surround sound encoding to Lt/Rt (D0:13DE) for Dolby Digital/DTS multichannel signals - Mixing and digital filtering for the different Output and Bass configurations according to the Dolby Digital Licensee Information Manual and one additional Bass Management Configuration called "Bass to Center" (D0:13D5, D0:13D6, D0:13DA). - Digital volume control (D0:13E1...13E8) for all audio formats - Appropriate delay lines for center and surround channels (D0:13D2...13D4) for Dolby Digital/DTS multichannel and Pro Logic II processed stereo signals L C R LS RS -5 dB LFE + SUB Fig. 2-3: Bass Management configuration 0 2.9.14.1. Extra Stereo Output For headphone and VCR recordings, a downmixed output is provided simultaneously to 5.1 multichannel output. The downmix can be switched from Lt/Rt (surround-encoded, default) to Lo/Ro (headphone encoded). Both, the 6-channel output and the Extra Stereo Output, are routed to the serial data output interface. Bass Management mode 1 (D0:13DA = 9) Attenuation of -15 dB in the SUB channel should be compensated by a 15 dB gain in the D/A-converter. L C R LS RS -15 dB x 5 L C R LS RS -5 dB LFE + SUB Note: In order to prevent clipping due to the downmixing in the Custom and Line Modes, the HighLevel Cut Compression Scale Factor (D0:13D8) must always be left at 7FFFFhex when the Extra Stereo Output is used in conjunction with nondownmixed channels (D0:13D6). Fig. 2-4: Bass Management configuration 1 Bass Management mode 2 (D0:13DA = Ahex) Level adjustment is implemented with -12 db. -12 dB -1.5 dB -12 dB Level Adj Level Adj -15 dB x 3 -5 dB -1.5 dB L + L C 2.9.14.2. Digital Volume The digital volume control provided is mainly intended for balancing purposes and initially set to 0 dB. Volume control, output configuration, and delays should be set by the controller according to the actual listening situation. C R LS RS LFE + Level Adj + R LS RS SUB Fig. 2-5: Implementation of configuration 2 16 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Bass Management mode 6 (D0:13DA = Ehex) L C R LS RS + Bass Management mode 3 (D0:13DA = Bhex) L C R LS RS -15 dB x 3 L C R LS RS -4.5 dB x 3 L C + R LS RS LFE -5 dB + SUB LFE + -5 dB + SUB Fig. 2-6: Alternative implementation of configuration 2 Fig. 2-9: Simplified Bass Management for Multichannel Source Products () Bass Management mode 4 (D0:13DA = Chex) Bass Management mode 7 (D0:13DA = Fhex) L C -4.5 dB + L C L C + + + + R LS RS SUB LFE R LS RS -4,5 dB x 3 L C R LS RS + -10.5 dB -5 dB R LS RS LFE Fig. 2-7: Implementation of configuration 3 with subwoofer + SUB Fig. 2-10: Simplified Bass Management for Multichannel Source Products () Bass Management mode 5 (D0:13DA = Dhex) The analog part of SUB should add a +10 db gain Bass Management mode Bass to Center (D0:13DA = 18hex) L C -4.5 dB L C + L C -15 dB -15 dB -15 dB -15 dB -15 dB -5 dB L + C R LS RS + R LS RS LFE + + + R LS RS SUB R LS RS LFE SUB Fig. 2-8: Implementation of configuration 3 Fig. 2-11: Bass to Center Mode (B2C) for TV Sets with large Center and small L / R / Ls / Rs Speakers. Micronas Dec. 4, 2003; 6251-598-2PD 17 MAS 35xyH 2.9.15. Output Format Selection The output is an I2S bus format with either eight audio channels on one line (default), or two audio channels on each of four lines (D0:13D0). If the 4x2 configuration is selected, the clock and word strobe lines SOC and SOI apply to all four data lines SOD...SOD3. Clock and word strobe signals can be configured to different standards (polarity, delay). The data word length is always 32 bits. In the 1x8 format, the output data are in the following order: L, LS, C, Lt/Lo, R, RS, Sub, Rt/Ro. PRELIMINARY DATA SHEET 2.10. System Interaction 2.10.1. Minimum Required Interconnections The MAS 35xyH requires the following connections for normal operation: - Power supply with adequate blocking capacitors (VDD, VSS, AVDD, AVSS, XVDD, XVSS) - Crystal with capacitors or clock input (XTI, XTO) - I2C bus and reset line (I2CC, I2CD) and reset line (POR) for controlling - S/PDIF input (SPDI/SPDI2, SPREF) or serial/I2S input (SID, SIC, SII or SID*, SIC*, SII*). In the standard Micronas solution, the I2S signal comes from the MSP 44x0G - I2S output (SOD, SOC, SOI). In the standard configuration, this signal is fed to the DPL 4519G. Please refer to Fig. 5-1 on page 69 or to the application kit for details. 2.9.16. S/PDIF Loop-Through By default, an undecodable signal is looped through. This means that the signal at S/PDIF input is routed to S/PDIF output without processing - regardless of bit 1 in register 2Ehex. This automatism can be disabled by setting bit 12 in register 2Ehex to "1". Now, the controller is to choose via bit 1, whether a PCM audio signal is output (in case of an undecodable signal the output is muted) or whether the input data is looped through. 2.10.2. Required Special Modes in the System The MAS 35xyH interfaces require no configuration. The I2S outputs and inputs of the DPL 4519G and the MSP 44x0G, however, must be configured to send/ accept the 8-channel multiplexed digital PCM data stream. The DPL 4519G may generate up to seven analog signals (three pairs plus subwoofer). Further audio signals can be forwarded to the MSP 44x0G for D/A conversion. Dolby Pro Logic encoded audio originating from the MSP 44x0G (TV sound) must be routed to the MAS 35xyH for Pro Logic II decoding. 2.9.17. Output Sampling Rate The internally generated system clock is derived from the filling status of the input data buffer by a PLL. This clock is synchronous to the original sampling rate and is used throughout the complete data processing. Except in the ambiguous case of PCM data at the serial audio input where the original sampling rate must be defined (D0:13DB), no controller interaction is needed for clock operation. The output sampling rate is 32 kHz, 44.1 kHz, or 48 kHz, depending on the source. Since in the Micronas Dolby Digital TV sound solution all further signal processing is on a rate of 48 kHz, the input stage of the DPL 4519G performs the sample rate conversion if necessary. 18 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Output (numbers 7 to 10 mean first to fourth pair) - Select one input pair as source for Aux Output (numbers 7 to 10 mean first to fourth pair) - Set volume control for Loudspeaker Output - Set volume control for Aux Output If there is a multistandard sound processor in the system, similar set-up commands are required. For further details, please refer to the DPL 4519G or the MSP 44x0G data sheets. If both devices are used on the same I2C bus, the device addresses must be set to different values by hardware means. The D/A conversion of audio signals may be freely appointed between the DPL 4519G and the MSP 44x0G. For an example, please see Table 2-3. 2.10.3. Minimum System Set-Up The following I2C command sequence is necessary for the DPL 4519G: - I2C-controlled reset - Write MODUS Register (set I2S input to slave mode) - Write I2S_CONFIG (multisample mode, 32 bits, clock to 8*32 bits) - Set I2S3 Resorting Matrix to "left/right eight MAS 35xyH". The signal pairs are now in the following order: Lt/Rt, L/R, SL/SR, C/Sub - Select first I2S 3-input pair as source for I2S Output (because of 8*32 bit mode all 4*2 channels will be looped through to the MSP 44x0G) and set to transparent stereo - Select one input pair as source for Loudspeaker Table 2-2: Output configuration matrix. All registers are at I2C subaddress 12hex of the respective device. Note that only one code per register applies. Device Register Signal Pair Lt/Rt (Lo/Ro) L/R SL/SR C/Sub 1) DPL 4519G Loudsp. 00 08hex 07 20hex 08 20hex 09 20hex 0A 20hex1) Aux 00 09hex 07 20hex 08 20hex 09 20hex 0A 20hex1) SCART1 00 0Ahex 07 20hex 08 20hex 09 20hex 0A 20hex1) Loudsp. 00 08hex 07 20hex 08 20hex 09 20hex 0A 20hex1) Aux 00 09hex 07 20hex 08 20hex 09 20hex MSP 44x0G SCART1 00 0Ahex 07 20hex 08 20hex 09 20hex 0A 20hex1) SCART2 00 41hex 07 20hex 08 20hex 09 20hex 0A 20hex1) 0A 20hex1) Use 0A 20hex for C/Sub output, 0A 00hex for Center signal on both outputs, 0A 10hex for Sub signal on both outputs Table 2-3: Example: In the DPL 4519G use both loudspeaker output channels for center, the auxiliary output for surround, the SCART1 output for Lt/Rt. In the MSP 44x0G use the loudspeaker output for L/R, both auxiliary output channels for Sub and the SCART1 output for an additional Lt/Rt-signal. Device Register Signal Pair Lt/Rt (Lo/Ro) L/R SL/SR C/Sub 0A 00hex 09 20hex 0A 10hex Loudsp. 00 08hex DPL 4519G Aux 00 09hex SCART1 00 0Aahex 07 20hex 08 20hex Loudsp. 00 08hex Aux 00 09hex MSP 44x0G SCART1 00 0Ahex 07 20hex SCART2 00 41hex Micronas Dec. 4, 2003; 6251-598-2PD 19 MAS 35xyH 3. Control Interface 3.1. Start-Up Sequence After power-up and a reset (see Section 3.3. on page 21), the IC is in its default state (see Table 3-7 on page 38). The controller has to initialize all memory cells for which a non-default setting is necessary. 3.2. I2C Interface Access 3.2.1. General Control communication with the MAS 35xyH is done via an I2C slave interface. The device addresses are 3Ahex (write) and 3Bhex (read) as shown in Table 3-1. I2C clock synchronization is used to slow down the interface if required. Table 3-1: I2C device address A7 0 A6 0 A5 1 A4 1 A3 1 A2 0 A1 1 W/R 0/1 PRELIMINARY DATA SHEET 3.2.3. Conventions for the Command Description The description of the various controller commands uses the following formalism: - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - A data value is split into 4-bit nibbles which are numbered zero-bound. - Data values in nibbles are always shown in hexadecimal notation. - A hexadecimal 20-bit number d is written, e.g. as d = 17C63hex, its five nibbles are d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and d4 = 1hex. - Variables used in the following descriptions: dev_write 3Ahex device write dev_read 3Bhex device read data_write 68hex data register write data_read 69hex data register read control 6Ahex control register write - Bus signals S Start P Stop A ACK = N NAK = W Wait = 3.2.2. I2C Registers and Subaddresses The interface uses one level of subaddresses. The MAS 35xyH interface has 3 subaddresses allocated for the corresponding I2C registers. The address 6Ahex is used for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 35xyH. The I2C control and data registers of the MAS 35xyH are 16 bits wide, the MSB is denoted as bit [15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus for each register access two 8-bit data words must be sent or received via I2C bus. Table 3-2: Subaddresses Subaddress 68hex 69hex 6Ahex I2CRegister data data control Function Controller writes to MAS 35xyH data register Controller reads from MAS 35xyH data register Controller writes to MAS 35xyH control register Acknowledge Not acknowledge I2C clock line is held low while the MAS 35xyH is processing the current I2C command - Symbols in the telegram examples < Start Condition > Stop Condition dd data byte xx ignore All telegram numbers are hexadecimal, data originating from the MAS 35xyH are shown in gray. Example: <3A 68 dd dd> write data to DSP <3A 69 <3B dd dd> read data from DSP Fig. 3-1 shows I2C bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with the read command (3Bhex). Fields with signals/data originating from the MAS 35xyH are marked by a gray background. Note that in some cases, the data reading process must be concluded by a NAK condition. 20 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Example: I2C write access S dev_write (3Ahex) W A data_write (68hex) A high data word A low data word A P Example: I2C read access S dev_write (3Ahex) W A data_read (69hex) A S dev_read (3Bhex) W A high data word low data word SDA SCL S 1 0 A N P P W = Wait A = 0 - Acknowledge (Ack) N = 1 - Not Acknowledge (NAK) S = Start P = Stop Fig. 3-1: I2C bus protocol for the MAS 35xyH (MSB first; data must be stable while clock is high) 3.2.4. The Internal Fixed Point Number Format In the following sections, two number representations are used: The fixed point notation `v' and the 2's complement number notation `r'. The conversion between the two forms of notation is easily done (see the following equations). r = v*524288.0+0.5; (-1.0 v < 1.0) v = r/524288.0; (-524288 < r < 524287) 3.3. I2C Control Register (Code 6Ahex) S dev_write W A control A d3,d2 A d1,d0 A P 3.4. I2C Data Register (Codes 68hex and 69hex) and the MAS 35xyH DSP-Command Syntax The DSP core of the MAS 35xyH has two RAM-banks denoted D0 and D1. The word size is 20 bits. All RAMaddresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For fast access of internal DSPstates, the processor core also has an address space of 256 data registers. All register and RAM addresses are given in hexadecimal notation. The control of the DSP in the MAS 35xyH is done via the I2C data register by using a special command syntax. These commands allow the controller to access the DSP registers and RAM cells and thus monitor internal states, set the parameters for the DSP firmware, control the hardware, and even provide a download of alternative software modules. The DSP commands consist of a "Code" which is sent to I2C data register together with additional parameters. S dev_write W A data_write A Code,... A ...,... A ... (EQ 1) (EQ 2) The I2C control register is a write-only register. Its main purpose is the software reset of the MAS 35xyH. The software reset is done by writing a 16-bit word to the MAS 35xyH with bit 8 set. The four least significant bits are reserved for task selection. In standard Dolby Digital/MPEG-decoding, these bits must always be set to 0. Table 3-3: Control register bit assignment1) 15 x 14 x 13 x 12 x 11 x 10 x 09 x 08 R 07 0 06 0 05 0 04 0 03 T3 02 T2 01 T1 00 T0 1) x = don't care, R = reset, T3...T0 0 task selection The MAS 35xyH firmware scans the I2C interface periodically and checks for pending or new commands. The commands are then executed by the DSP during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. However, due to some time critical firmware parts, a certain latency time for the response has to be expected. The theoretical worst case response time does not exceed 4 ms. However, the typical response time is less than 0.5 ms. Table 3-4 on page 22 shows the basic controller commands that are available by the MAS 35xyH. Micronas Dec. 4, 2003; 6251-598-2PD 21 MAS 35xyH PRELIMINARY DATA SHEET Table 3-4: Basic controller command codes Code (hex) A B C D E F Command Read from register Write to register Read D0 memory Read D1 memory Write D0 memory Write D1 memory Function Controller reads an internal register of the MAS 35xyH. Controller writes an internal register of the MAS 35xyH. Controller reads a block of the DSP memory. Controller reads a block of the DSP memory. Controller writes a block of the DSP memory. Controller writes a block of the DSP memory. Table 3-4 gives an overview of the different commands which the DSP-core may receive. The "Code" is always the first data nibble transmitted after the "data_write" byte. A second auxiliary code nibble is used for the short memory access commands. Because of the 16-bit width of the I2C-data register, all actions always transmit telegrams with multiples of 16 data bits. 22 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 3.4.3. Read Memory (Codes Chex and Dhex) The MAS 35xyH has 2 memory areas called D0 and D1. Both areas have different read and write commands. The memory areas D0 can be read by using the codes Chex. 1) send command (e.g. Read D0) S dev_write W A data_write A C,0 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 3.4.1. Read Register (Code Ahex) 1) send command S dev_write W A data_write A A,r1 A r0,0 W A P 2) get register value S dev_write W x,x A A data_read A x,d4 W A S dev_read W A A W N P d3,d2 d1,d0 The MAS 35xyH has an address space of 256 DSPregisters. Some of the registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others control the internal program flow. In Section 3.5. on page 25, the registers of interest with respect to the Dolby Digital/MPEG-decoding firmware are described in detail. In contrast to memory cells, registers cannot be accessed as a block but must always be addressed individually. Example: Read the content of register (2Ehex): <3A 68 A2 E0> <3A 69 <3B xx xd dd dd> define register and read 2) get memory value S dev_write W x,x A A data_read A x,d4 W A S dev_read W A A W A d3,d2 d1,d0 ....repeat for n data values.... x,x A x,d4 W A d3,d2 A d1,d0 W N P The Read D0 Memory command gives the controller access to all 20 bits of D0-memory cells of the MAS 35xyH. The telegram to read three words starting at location D0:100 is <3A 68 C0 00 00 03 01 00> <3A 69 <3B xx xd dd dd xx xd dd dd xx xd dd dd> The Read D1 Memory command (Dhex)is provided to get information from D1 memory cells of the MAS 35xyH. 3.4.2. Write Register (Code Bhex) S dev_write W A data_write A B,r1 d3,d2 A A r0,d4 d1,d0 W W A A P The controller writes the 20-bit value (d = d4,d3,d2,d1,d0) into the MAS 35xyH register (r = r1,r0). A list of registers is given in Section 3.5. on page 25 Example: Disable automatic S/PDIF loop-through for DTS by writing the value 1000hex into the register with the number 2Ehex: <3A 68 B2 E0 10 00> 3.4.4. Short Read Memory (Codes C4hex and D4hex) Because most cells in the Dolby Digital user interface are only 16 bits wide, it is faster and more convenient to access the memory locations with a special 16-bit mode for reading: 1) send command (e.g. Short Read D0) S dev_write W A data_write A C,4 n3,n2 a3,a2 A A A 0,0 n1,n0 a1,a0 W W W A A A P 2) get memory value S dev_write W A data_read A S dev_read W A A W A d3,d2 d1,d0 ....repeat for n data values.... d3,d2 A d1,d0 W N P This command is similar to the normal 20-bit read command and uses the same command codes Chex and Dhex for D0 and D1-memory, respectively, however, it is followed by a 4hex rather than a 0hex. Micronas Dec. 4, 2003; 6251-598-2PD 23 MAS 35xyH The Short Read D1 Memory command works similarly to the Read D1 Memory command but with the code Dhex followed by a 4hex. Example: Read 16 bits of D1:123 has the following I2C protocol: <3A 68 D4 00 00 01 01 23> <3A 69 <3B dd dd> read 16 bits from D1 one word to be read start address start reading PRELIMINARY DATA SHEET 3.4.6. Short Write Memory (Codes E4hex and F4hex) e.g. Short Write D0 S dev_write W A data_write A A A A E,4 n3,n2 a3,a2 d3,d2 A A A A 0,0 n1,n0 a1,a0 d1,d0 W W W W A A A A ....repeat for n data values.... A d3,d2 A d1,d0 W A P 3.4.5. Write Memory (Codes Ehex and Fhex) The memory areas D0 and D1 can be written by using the codes Ehex and Fhex, respectively. e.g. Write D0 S dev_write W A data_write A E,0 n3,n2 a3,a2 0,0 d3,d2 A A A A A 0,0 n1,n0 a1,a0 0,d4 d1,d0 W W W W W A A A A A For faster access, only the lower 16 bits of each memory cell are accessed. The four MSBs of the cell are cleared. The command uses the same codes Ehex and Fhex for D0/D1 as for the 20-bit command but followed by a 4 rather than a 0. 3.4.7. Default Read The Default Read command is the fastest way to get information from the MAS 35xyH. Executing the Default Read in a polling loop can be used to detect a special state during decoding. ....repeat for n data values.... 0,0 d3,d2 A A 0,d4 d1,d0 W W A A P S DW W A data_read A S dev_read W d3,d2 A A d1,d0 W N P With the Write D0/D1 Memory command n 20-bit memory cells in D0/D1 can be initialized with new data. Example: Write 80234hex to D0:FFB has the following I2C protocol: <3A 68 E0 00 0F 00 02 00 01 Fb 08 34> write D0 memory 1 word to write start address FFBhex value = 80234hex The Default Read command immediately returns the lower 16 bit content of a specific RAM location as defined by the pointer D0:FFB. The pointer must be loaded before the first Default Read action occurs. If the MSB of the pointer is set, it points to a memory location in D1 rather than to one in D0. Example: For watching D1:123, the pointer D0:FFB must be loaded with 8123hex: <3A 68 00 0F 00 01 E0 00 01 Fb 08 23> write to D0 memory one word to write start address FFB value = 8hex... ...0123hex Now the Default Read commands can be issued as often as desired: <3A 69 <3B dd dd> Default Read command 16 bit content of the address as defined by the pointer ... and do it again <3A 69 <3B dd dd> 24 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 3.5. Registers In Table 3-5, the internal registers that are useful for controlling the MAS 35xyH are listed. They are accessible by Read/Write Register I2C commands (see Section 3.4.1. and Section 3.4.2. on page 23). Note: Registers not given in this table must not be written. Table 3-5: Command Register Table Register Address (hex) 2E W R/W Function Default (hex) S/PDIF-Input 00000 Name Loop-through and Sync Pin Control bit[12] Output_Conf 0: automatic active loop-through if the input format at S/PDIF_in cannot be determined (default) 1: bit[1] controls loop-through reserved: do not change! 0: normal operation 1: connect SPDI_in to SPDIF OUT (loop-through) sync bit in case of AC-3 and MPEG signals, this bit will be automatically detected and set by internal software, it will not be set by PCM signals. 00000 PIO_Config W bit[11:2] bit[1] R bit[0] 4B W PIO Configuration Configuration of pins must be zero. 48 R PIO Data Input The input level of every PI pin in the input mode can be read out of this register; the bit number corresponds to the PI number. bit[n] bit[n] 0: input is low 1: input is high PIO_Data_In 49 W PIO Data Output The output level of every PI pin in the output mode can be defined by this register; the bit number corresponds to the PI number. bit[n] bit[n] 0: output is low 1: output is high PIO_Data_Out Micronas Dec. 4, 2003; 6251-598-2PD 25 MAS 35xyH Table 3-5: Command Register Table, continued Register Address (hex) CC R/W Function PRELIMINARY DATA SHEET Default (hex) 00000 Name R/W PIO Direction Every bit switches the PI pin with the corresponding number from input to output. bit[n] bit[n] bit[14:16] 0: input mode 1: output mode must be zero if PI14, PI15, and PI16 are used as alternative inputs SID*, SII*, and SIC*. S/PDIF-Input PIO_Direction 56 R Incoming S/PDIF Channel Status Bits bit[19:0] SPI0CS mirrors first 20 channel status bits 26 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 3.6.1. Status Interface for Decoding The following table contains the memory locations of the firmware status information. Addresses are hexadecimal, memory cell content is binary when written without indicator and hexadecimal when written with a hex-suffix. 3.6. Special Memory Locations and User Interface Operation of the DSP and the interfaces can be observed and controlled via the memory locations of the user interface. These memory cells are located at the high end of the D0-RAM. Status cells are written by the DSP and read by the controller, configuration cells are written by the controller and read by the DSP, hybrid cells can be written and read by either side. Note: Memory addresses not given in this table must not be accessed. Table 3-6: Status memory cells Memory Address (hex) D0:13A0 Function Mode Name Sample Rate of Input Bitstream (Table 5.1 of ATSC Spec. A/52) Dolby Digital DTS MPEG PCM UIS_FSCOD bit[1:0] 00 01 10 11 48 kHz 44.1 kHz 32 kHz not detected (default) Dolby Digital UIS_BSID D0:13A1 Bit Stream Identification (bsid) (Section 5.4.2.1 of ATSC Spec. A/52) bit[4:0] 00hex...1fhex current bsid value Bit streams that have a bsid higher than the decoder's version number may be incompatible. In this case, the decoding is inhibited. The version number for the implemented firmware is 8. Bit Stream Identification (bsid) bit[3:0] 0hex...fhex current bsid value DTS Bit streams that have a bsid higher than the decoder's version number may be incompatible. In this case, the decoding is inhibited. The version number for the implemented firmware is 7. Revision 0 - 6 will be compatible with this specification. Revision 8 -15 will be incompatible with this specification. Note: see description of D0:13d0 bit 17 Micronas Dec. 4, 2003; 6251-598-2PD 27 MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13A2 Function PRELIMINARY DATA SHEET Mode Name Bit Stream Mode (bsmod) (Table 5.2 of ATSC Spec. A/52) bit[2:0] 000 001 010 011 100 101 110 111 111 Dolby Digital UIS_BSMOD main audio service: complete main (CM) main audio service: music and effects (ME) associated service: visually impaired (VI) associated service: hearing impaired (HI) associated service: dialogue (D) associated service: commentary (C) associated service: emergency (E) acmod = 001, associated service: voice over (VO) acmod = 010-111, main audio service: karaoke This information is valid after selecting (D0:13D0) an available (D0:13BC) channel (data stream) from the S/PDIF input. Prior to this, the bsmod can be directly derived from the Pc-preambles of the S/PDIF-data (D0:13BD...13C4). D0:13A3 Audio Coding Mode (acmod) (Table 5.3 of ATSC Spec. A/52) DD: DTS: bit[2:0] 000 001 010 011 100 101 110 111 1+1 1/0 2/0 3/0 2/1 3/1 2/2 3/2 bsmod != '111' this column Ch1, Ch2 C L, R L, C, R L, R, S L, C, R, S L, R, SL, SR L, C, R, SL, SR Dolby Digital DTS bsmod = '111' (Karaoke) Voice Over (VO) L, R L, M, R L, R, V1 L, M, R, V1 L, R, V1, V2 L, M, R, V1, V2 UIS_ACMOD For user information: indicates the applied main channel. D0:13A4 Center Mix Level (cmixlev) (Table 5.4 of ATSC Spec. A/52) bit[1:0] 00 01 10 11 Dolby Digital UIS_CLEV 0.707 (-3.0 dB) 0.595 (-4.5 dB) 0.500 (-6.0 dB) reserved (-6.0 dB), nominal downmix level of center with respect to left and right channels Used in the internal algorithm. D0:13A5 Surround Mix Level (surmixlev) (Table 5.5 of ATSC Spec. A/52) bit[1:0] 00 01 10 11 Dolby Digital UIS_SLEV 0.707 (-3.0 dB) 0.500 (-6.0 dB) 0 reserved (-6.0 dB), nominal downmix level of surround channels Used in the internal algorithm. 28 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13A6 Function Mode Name Dolby Surround Mode (dsurmod) (Table 5.6 of ATSC Spec. A/52) bit[1:0] 00 01 10 11 not indicated not Dolby Surround encoded Dolby Surround encoded reserved (not indicated) Dolby Digital DTS UIS_DSURMOD As soon as the audio is Dolby Surround encoded, the controller must activate the Dolby Pro Logic decoder (e.g. in the DPL 4519G) without any user interaction. D0:13A7 Low Frequency Effects Channel (lfeon) (Section 5.4.2.7 of ATSC Spec. A/52) bit[0] 0 1 LFE off LFE on Dolby Digital DTS UIS_LFEON The user may want to choose a different output configuration depending on the availability of the LFE. D0:13A8 Dialogue Nomalization (dialnorm) (Section 5.4.2.8 of ATSC Spec. A/52) 00hex reserved 01hex... -1 dBFS... 1Fhex -31dBFS average dialog level Used in the internal algorithm. D0:13AA Language Code (langcode, langcod) (Sections 5.4.2.11 and 5.4.2.12 of ATSC Spec. A/52) bit[15:0] bit[7:0] FFFFhex Dolby Digital UIS_LANGCOD bit[4:0] Dolby Digital DTS UIS_DIALNORM langcode = 0 (langcod nonexistent in stream) langcod The controller may check all S/PDIF data streams (channels) for the desired language. D0:13AB Mixing Level and Room Type Dolby Digital (audprodie, mixlevel, roomtyp) (Sections 5.4.2.13, 5.4.2.14 and 5.4.2.15 of ATSC Spec. A/52) bit[15:0] bit[6:2] bit[1:0] For user information. D0:13AC Dialogue Nomalization 2 for Dual Mono Mode 1+1 (dialnorm2) (Section 5.4.2.16 of ATSC Spec. A/52) bit[4:0] 01hex...1Fhex average dialog level -1dB...-31dB below 100% digital 00hex reserved Dolby Digital UIS_DIALNORM2 FFFFhex audprodie = 0 (mixlevel, roomtyp nonexistent in data stream) mixlevel roomtyp UIS_MIXLEVEL_ ROOMTYP Used in the internal algorithm. Micronas Dec. 4, 2003; 6251-598-2PD 29 MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13AE Function PRELIMINARY DATA SHEET Mode Name Language Code 2 for Ch2 in Dual Mono Mode 1+1 (langcod2e, langcod2) (Section 5.4.2.19 and 20 of ATSC Spec. A/52) bit[15:0] bit[7:0] FFFFhex Dolby Digital UIS_LANGCOD2 langcod2e = 0 (langcod2 nonexistent in stream) langcod2 Used in the internal algorithm. D0:13AF Mixing Level and Room Type for Ch2 in Dolby Digital Dual Mono Mode 1+1 (audprodi2e, mixlevel2, roomtyp2) (Section 5.4.2.21, 22 and 23 of ATSC Spec. A/52) bit[15:0] bit[6:2] bit[1:0] For user information. D0:13B0 Copyright Bit (copyrightb) (Section 5.4.2.24of ATSC Spec. A/52) bit[0] D0:13B1 0 1 Dolby Digital DTS UIS_COPYRIGHT B FFFFhex audprodi2e = 0 (mixlevel2, roomtyp2 nonexistent in stream) mixlevel2 roomtyp2 UIS_MIXLEVEL2_ ROOMTYP2 not protected protected by copyright (copy prohibited) Dolby Digital UIS_ORIGBS Original Bit Stream (origbs) (Section 5.4.2.25 of ATSC Spec. A/52) bit[0] 0 1 copy of a bit stream original bit stream Original Bit Stream (origbs) 01 10 11 valid if copyrightb = 0 D0:13B2 bit[1..0] first generation second generation original bit stream DTS Time Code 1 (Section 5.4.2.27of ATSC Spec. A/52) bit[15:0] bit[13:0] bit[13:9] bit[8:3] bit[2:0] FFFFhex Dolby Digital DTS UIS_TIMECOD1 timecod1e = 0 (time code 1 nonexistent) time code 1(first half) time in hours (0...23 valid) time in minutes (0...59 valid) time in 8-second increments (0 = 0 seconds) (1 = 8 seconds) : (7 = 56 seconds) For external synchronization purposes. Note: DTS: if TIMEF = 0 this value will always be FFFFhex 30 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13B3 Function Mode Name Time Code 2 (Section 5.4.2.28of ATSC Spec. A/52) bit[15:0] bit[13:0] bit[13:11] bit[10:6] bit[5:0] FFFFhex Dolby Digital DTS UIS_TIMECOD2 timecod2e = 0 (time code 2 nonexistent) time code 2 (second half) time in 8-second increments, see time code 1 time in frames (0...29 valid) time in 1/6 frames For external synchronization purposes. Note: DTS: if TIMEF = 0 this value will always be FFFFhex D0:13B4 Dynamic Range Gain Word (dynrnge, dynrng) (Section 5.4.3.3 and 5.4.3.4 of ATSC Spec. A/52) bit[15:0] bit[7:0] FFFFhex Dolby Digital UIS_DYNRNG dynrnge = 0 (dynrng nonexistent in stream) current dynrng / RANGE value Used in the internal algorithm. Dynamic Range Gain Word (dynf, RANGE) bit[15:0] bit[19:0] D0:13B5 FFFFhex dynf nonexistent in stream current RANGE value (15bit mantissa, 4bit exp.) Dolby Digital UIS_DYNRNG2 DTS Dynamic Range Gain Word 2 for Ch2 in dual mono mode (dynrng2e, dynrng2) (Section 5.4.3.5 and 5.4.3.6 of ATSC Spec. A/52) bit[15:0] bit[7:0] FFFFhex dynrng2e = 0 (dynrng2 nonexistent in stream) current dynrng value Used in the internal algorithm. D0:13B6 Karaoke Flag bit[0] AUX bit[12:0] bit[18:13] bit[19] D0:13B7 Memory address of auxiliary data bytes Auxiliary data byte count. Present if auxiliary data bytes are appended at end of frame Auxiliary data flag Dolby Digital MPEG DTS counts 0, 1, 2, 3, 4, ..., 1048575 (= FFFFFhex), 1, ... UIS_FRAME_ COUNTER 0 1 no Karaoke info in bit stream Karaoke info in bit stream DTS Dolby Digital UIS_ KARAOKEFLAG UIS_AUX Frame Count bit[19:0] Micronas Dec. 4, 2003; 6251-598-2PD 31 MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13B8 Function PRELIMINARY DATA SHEET Mode Name MPEG Header Bits 12...31 bit[19] bit[18:17] 00 01 10 11 bit[16] 0 1 bit[15:12] 0hex 1 2 3 4 5 6 7 8 9 a b c d e f bit[11:10] 00 01 10 11 ... ID (must be 1 for MPEG-1) Layer reserved Layer 3 Layer 2 Layer 1 Protection CRC no CRC bit rate (see table in IEC 11172-3, Layer 2) free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden sampling frequency (MPEG-1 Layer-2) 44.1 kHz 48 kHz 32 kHz reserved MPEG UIS_MPEG_ HEADER 32 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13B8 (continued) Function Mode Name bit[9] bit[8] bit[7:6] 00 01 10 11 bit[5] 0 1 bit[4] 0 1 bit[3] 0 1 bit[2] 0 1 bit[1:0] 00 01 10 11 padding bit private bit Mode stereo joint stereo dual channel reserved Joint Stereo Mode Extension ms_stereo off on Joint Stereo Mode Extension Intensity Stereo off on Copyright not protected protected Original/Copy copy original Emphasis none 50/15 s reserved CCITT J.17 Micronas Dec. 4, 2003; 6251-598-2PD 33 MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13B8 (continued) PRELIMINARY DATA SHEET Function Mode Name Protection (CPF) bit[11] RATE bit[10:6] 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex 09hex 0ahex 0bhex 0chex 0dhex 0ehex 0fhex 10hex 11hex 12hex 13hex 14hex 15hex 16hex 17hex 18hex 19hex 1ahex 1bhex 1chex 1dhex 1ehex 1fhex 32 kbps 56 kbps 64 kbps 96 kbps 112 kbps 128 kbps 192 kbps 557 kbps 256 kbps 320 kbps 384 kbps 448 kbps 512 kbps 576 kbps 640 kbps 768 kbps 960 kbps 1024 kbps 1152 kbps 1280 kbps 1344 kbps 1408 kbps 1411.2 kbps 1472 kbps 1536 kbps 1920 kbps 2048 kbps 3072 kbps 3840 kbps open variable lossless 0 1 no CRC CRC DTS UIS_DTS_ HEADER PCMR bit[5:1] 10hex 14hex 18hex 16 bits 20 bits 24 bits DTS HDCD bit[0] D0:13B9 copy of HDCD in bit stream DTS MPEG Status bit[5] bit[4] bit[3:2] bit[1:0] 0 1 1 >0 >0 mono stereo CRC error other decoding error (not enough data) header error MPEG UIS_MPEG_ STATUS 34 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13BB Function Mode Name Global Operation Status (GOS) bit[7:5] GOS_Type 0 1 2 3 4...6 7 Appl_Type 0 1 2 3 4 5 15 0 1 All UIS_GOS GOS_NODEC, not decodable GOS_PCM_WARN, channel status not plausible GOS_DATA, data type GOS_PCM reserved GOS_I2S AC-3 MPEG Layer-2 PCM time code noise generator DTS unknown unsynchronized (default) valid bit stream detected bit[4:1] bit[0] This status cell reflects the result of the decoding with the parameters given. If an incorrect input data type (D0:13D0) is selected, the input data stream will not be decodable. The GOS_PCM_WARN-flag is set when the S/PDIF-channel status indicates PCM-encoded audio, but valid synchronization headers (Dolby Digital or MPEG) are found. D0:13BC Bit Stream Information each bit: bit[7] ... bit[0] 1 0 channel available channel not available bit stream number 7 bit stream number 0 S/PDIF-Input UIS_DSI Available bit streams (channels) in the S/PDIF-data. Micronas Dec. 4, 2003; 6251-598-2PD 35 MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13BD ... D0:13C4 Function PRELIMINARY DATA SHEET Mode Name Pc Information of Selected Data Stream (burst_info) (Section 4.4.3 of Annex B of ATSC Spec. A/52) bit[15:13] bit[12:8] bit[7] 0 1 bit[6:5] bit[4:0] 0hex...7hex S/PDIF-Input UIS_PC, i = 0...7 channel number (data_stream_number) data_type_dependent, see below error flag (error_flag) data may be valid data burst may contain errors reserved 00hex reserved 01hex AC-3 data 02hex reserved 03hex pause 04hex MPEG Layer-1 05hex MPEG-1 Layer-2, 3, or MPEG-2 without extension 06hex MPEG-2 data with extension 07hex reserved 08hex MPEG-2 Layer-1 low fs 09hex MPEG-1 Layer-2, 3 low fs 0Ahex reserved 0Bhex....Dhex. DTS 0Ehex....1Fhex.reserved This memory cell mirrors the Pc-word of the S/PDIF-preamble (burst_info) of the selected of eight possible data streams (channels) if available. Meaning of Field data_type_dependent AC-3: (Section 4.7 of Annex B of ATSC Spec. A/52) bit[12,11] bit[10:8] 00 reserved, shall be '00' value of bsmod as described in D0:13A2 Dolby Digital 36 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-6: Status memory cells, continued Memory Address (hex) D0:13C7 Function Mode Name S/PDIF Status bit[15] S/PDIF Input is synchronized while processing I2S S/PDIF-Input UIS_SP_STATUS D0:13D0 [9] = 0 S/PDIF Input selected 0 bit is always 0 (to be compatible with MAS 3528E) D0:13D0 [9] = 1 IS Input selected 0 S/PDIF Input not synchronized; no valid bit stream 1 S/PDIF Input in sync; valid bit stream. Further information about the signal can be obtained from UIS_DSI and UIS_PC; i=0..7. bit[3:2] Parity Error (only valid when processing S/PDIF Input) 0 no error >0 parity error Data Mode 0 PCM 1 compressed audio data S/PDIF Copy Active 0 inactive 1 active All MAS 3530H-C6 MAS 3529H-C6 MAS 3527H-C6 All UIS_MASH_ VERSION UIS_MASH_TYPE bit[1] bit[0] D0:13FC MAS 35xyH Type bit[15:0] 30dec 29dec 27dec D0:1FF7 MAS 35xyH Version bit[15:0] 0201hex MAS 35xyH-B3 0203hex MAS 35xyH-C4 0206hex MAS 35xyH-C6 D0:1FFF Version Number Returns the version number of the ROM-code as ASCII All UIS_VERSION Micronas Dec. 4, 2003; 6251-598-2PD 37 MAS 35xyH 3.6.2. Control Interface for Decoding Operation The following table gives the writable memory addresses of the control interface for the decoding firmware. Table 3-7: Configuration memory cells Memory Address (hex) D0:13D0 Function Mode PRELIMINARY DATA SHEET Reset Value (hex) 00000 Name I/O Control Version Number Check bit[17] VerNum Check 0 DTS version number not checked 1 DTS version number checked for VerNum 0-7 bitstream is decoded; for VerNum 8-15 bitstream is not decoded All Soft Mute 0 1 Soft mute off Soft mute on DTS UIC_IO_CONTROL Soft Mute bit[15] This switch is provided for user-controlled fast audio mute. CRC Check bit[14] CRC1 0 1 CRC2 0 1 Dolby Digital MPEG CRC1 on CRC1 off CRC2 on CRC2 off bit[13] Dolby Digital: CRC1 protects the header and 3/5 of the data, CRC2 protects the remaining 2/5 of the data. It is recommended that both AC-3 CRCchecks are enabled which yields to an automatic mute upon detection of an error. However, under special operating conditions (noisy channel), it may be advantageous to turn one (preferably CRC2) or both CRC-checks off. In this case, it is important to decrease the listening volume to prevent hearing injuries and damages to the equipment. MPEG: For MPEG, only CRC1 is applied. It is recommended to enable CRC1 to avoid strong digital noise in case of deranged or unreliable signals. 38 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13D0 (continued) Function Mode Reset Value (hex) 00000 Name S/PDIF Channel Select bit[12:10] 000 ... 111 S/PDIF channel select Channel 0 Channel 7 S/PDIF UIC_IO_CONTROL The S/PDIF may carry up to eight channels of compressed audio. Their content is shown in the S/PDIF-Pc-preambles (D0:13B8...13BF). Input and Mode Selection bit[18, 7:6] 000 001 010 011 100 bit[9] 0 1 bit[8] 0 1 Input data type Auto-detection AC-3 (Dolby Digital) MPEG Layer-2 PCM DTS S/PDIF or I2S Input Select S/PDIF input I2S input I2S input select I2S input at SID (word mode) Continuous data stream at SID (SII connected to ground) All All Output Interface Mode I2S word strobe polarity bit[5] bit[5] bit[1] 0 1 0 1 0 1 low = right, high = left high = right, low = left default I2S output mode: invert word strobe I2S output channels 1 x 8 channels 4 x 2 channels The clock and word strobe outputs SOC and SOI apply to all 4 data outputs SOD...SOD3 I2S word strobe alignment WS changes at data word boundary WS changes one clock cycle in advance I2S word strobe alignment All bit[0] 0 1 Input Interface Mode bit[4] 0 1 WS changes at data word boundary WS changes one clock cycle in advance I2S word strobe polarity low = right, high = left high = right, low = left default invert clock bit[3] 0 1 bit[2] 0 1 Micronas Dec. 4, 2003; 6251-598-2PD 39 MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13D1 Function Mode PRELIMINARY DATA SHEET Reset Value (hex) 00000 Name Noise Generator All (Sec. 4.10.2 of Dolby Digital Licensee Information Manual Issue 3) bit[7] bit[6] 0 1 bit[5:0] 000001 000010 000100 001000 010000 100000 000000 0 1 Noise generator off Noise generator on Noise type White noise Band-pass shaped noise L C R LS RS LFE No channel selected UIC_NOISE By combining the appropriate bits, more than one channel can output noise. The noise type can be selected between white and bandpass filtered with a maximum between 500 and 1000 Hz. The required stepping actions have to be initiated by the controller. D0:13D2 Center Channel Delay (Sec. 4.10.1 of Dolby Digital LIM Issue 3) bit [2:0] 000 ... 101 0 ms 5 ms Dolby Digital DTS Dolby Pro Logic II 00001 UIC_SL_DELAY Dolby Digital DTS Dolby Pro Logic II 00000 UIC_C_DELAY D0:13D3 Left Surround Channel Delay (Sec. 4.10.1 of Dolby Digital LIM Issue 3 and Sec. 2.1.4 of Pro Logic II LIM Issue 1) Dolby Digital Pro Logic II bit[3:0] 0000 1111 all Modes Music Mode Matrix Mode 0 ms ... 15 ms Movie Mode PL Emulation 10 ms ... 25 ms For Dolby Pro Logic II in Movie and in Pro Logic Emulation Mode, the delay is automatically extended by 10 ms. D0:13D4 Right Surround Channel Delay (Sec. 4.10.1 of Dolby Digital LIM Issue 3 and Sec. 2.1.4 of Pro Logic II LIM Issue 1) Dolby Digital Pro Logic II bit[3:0] 0000 1111 all Modes Music Mode Matrix Mode 0 ms ... 15 ms Dolby Digital DTS Dolby Pro Logic II 00000 UIC_SR_DELAY Movie Mode PL Emulation 10 ms ... 25 ms For Dolby Pro Logic II in Movie and in Pro Logic Emulation Mode, the delay is automatically extended by 10 ms. 40 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13D5 Function Mode Reset Value (hex) 00001 Name LFE Channel Enable bit[0] 1 0 Dolby Digital DTS Route LFE Channel to subwoofer output (if it exists in stream) enable LFE disable LFE UIC_OUT_LFE The subwoofer output is assembled from the LFE and the other channels depending on the Output Configuration. This switch disables only content coming from the LFE. D0:13D6 Output Mode Control (Downmix) (Section 7.8 of ATSC Spec. A/52) bit[4:3] Dolby Digital DTS Dolby Pro Logic II 00007 UIC_OUT_MODE_ CTRL 00 01 10 11 bit[2:0] Dual mono setting of Dolby C decoder, applicable only if Audio Coding Mode is dual mono (acmod = 0). The actual mixing depends on the number of available output channels (speakers). Stereo (straight output of both channels) Left Mono (channel 1) Right Mono (channel 2) Mixed Mono (sum of both channels) Listening Mode Selector Defines the number of available (desired) output channels (loudspeakers). 2/0 L, R Dolby Surround compatible 1/0 C 2/0 L, R 3/0 L, C, R 2/1 L, R, S 3/1 L, C, R, S 2/2 L, R, SL, SR 3/2 L, C, R, SL, SR 000 001 010 011 100 101 110 111 These downmixing options are independent of the setting of the Extra Stereo Output (D0:13DE). Undesired channels can be muted by setting the volume to zero or by muting the outputs in the DPL 4519G or MSP 44x0G, respectively. Only listening modes 1/0, and 2/0 should be used if dual mono is transmitted. Note: other values or combinations of bits must not be written, bits not mentioned must be set to 0. Micronas Dec. 4, 2003; 6251-598-2PD 41 MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13D7 Function Mode PRELIMINARY DATA SHEET Reset Value (hex) 00001 Name Compression Control Dolby Digital (Operational Modes, Dialog Normalization) (Sec. 3.7 of Dolby Digital Licensee Information Manual, Issue 3) bit[1:0] 00 01 10 11 Setting of Dolby C decoder Custom Mode 0 (analog dialog normalization) Custom Mode 1 (internal digital dialog normalization) Line Mode Compression RF out UIC_ COMPRESSION_ CONTROL The implemented dynamic range compression uses the transmitted variables dynrng, compr, and dialnorm. In Line Mode and in the Custom Modes, the dynamic compression may be scaled down by using the user-controlled high-level cut and low-level boost factors. Note that in Custom Mode 0, the effect of dynrng must be implemented in the analog part of the audio equipment. Note that in the Custom Mode downmix, an internal digital attenuation of 11 dB is applied that must be compensated externally. D0:13D8 High-Level Cut Compression Scale Factor Dolby Digital (Sec. 3.7 and Sec. 4.11.9 of Dolby Digital Licensee Information Manual, Issue 3) bit[19:0] 00000hex (full dynamic)...7FFFFhex (full compression) 7FFFF UIC_CUT_X This factor scales down potential attenuation (i.e. dynamic compression) of loud portions of the audio as defined by dynrng. High-Level Cut is only used in Line Mode (except in downmix) and in the Custom Modes. Note: In order to prevent clipping due to the downmixing in the Custom and Line Modes, the High-Level Cut Compression Scale Factor must always be left at 7FFFFhex when the Extra Stereo Output (D0:13DE) is used in conjunction with non-downmixed channels (D0:13D6). Please refer to section 4.5.8. of Dolby Digital Licensee Information Manual, Issue 3. D0:13D9 Low-Level Boost Compression Boost Factor Dolby Digital (Sec. 3.7 and Sec. 4.11.9 of Dolby Digital Licensee Information Manual, Issue 3) bit[19:0] 00000hex (full dynamic)...7FFFFhex (full compression) 7FFFF UIC_BOOST_Y This factor scales down potential amplification (i.e. dynamic compression) of weak portions of the audio as defined by dynrng. LowLevel Boost is only used in Line Mode and in the Custom Modes. 42 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13DA Function Mode Reset Value (hex) 00000 Name Bass Management All (see chapter 2.9.10.3.;Sec. 4.7 of Dolby Digital Licensee Information Manual Issue 3) bit[4:0] 00000 01000 01001 01010 01011 01100 01101 01110 01111 11000 Direct loop-through of all six channels without channel mixing Dolby Configuration 0 Dolby Configuration 1 Dolby Configuration 2 Dolby Alternative Configuration 2 Dolby Configuration 3 (No SubwooferOut) Dolby Configuration 3 (Subwoofer Out) Multichannel Source Products () Multichannel Source Products () B2C (Bass to Center) UIC_POST_ PROCESSING Note: If Bass Management is enabled, high processor clock must be selected (D0:13DF; bit16=1) The LFE-content can be disabled in D0:13D5. The output configurations can be used for all input formats. However, for MPEG and PCM-data, only the L and R input channels will carry information. Cross-Over Frequency (LP and complementary HP) bit[15:8] 0dec 5dec 10dec 15dec 20dec 25dec 30dec 35dec 40dec D0:13DD Karaoke Mode bit[1:0] 00 01 10 11 100 Hz (compatible with Type 2) 50 Hz 100 Hz 150 Hz 200 Hz 250 Hz 300 Hz 350 Hz 400 Hz min. cross-over frequency. All UIC_CROSSOVER _FREQ max. cross-over frequency Dolby Digital 00003 UIC_KARAOKE_ MODE no vocals vocal 1 vocal 2 vocal 1 (left) + vocal 2 (right) Dolby Digital (surround encoded) 00000 D0:13DE Extra Stereo Output (Lt/Rt or Lo/Ro) bit[0] 0 1 Lt/Rt stereo output Lo/Ro stereo output UIC_DOWNMIX_ MODE For headphone operation, the 2-channel output can be switched to the Lo/Ro-mode. Note: In order to prevent clipping due to the downmixing in the Custom and Line Modes, the High-Level Cut Compression Scale Factor (D0:13D8) must always be left at 7FFFFhex when the Extra Stereo Output is used in conjunction with non-downmixed channels (D0:13D6). Micronas Dec. 4, 2003; 6251-598-2PD 43 MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13DF Function Mode PRELIMINARY DATA SHEET Reset Value (hex) 80004 Name Output Clock Scaling bit[19] 0 1 bit[18:17] CLKO off enable CLKO disable CLKO Division factor applied to the internal reference clock (see Table 2-2 on page 19) for the CLKO-output divide reference clock by 1 divide by 2 divide by 4 divide by 8 All UIC_OUT_CLK_ SCALE 0 1 2 3 bit[16] 0 1 Low/high system clock for Dolby Digital (please refer to Table 2-1 on page 10) 61/56/40 MHz for 48/44.1/32 kHz 73/67/49 MHz for 48/44.1/32 kHz Sets the processor clock and the output clock at pin CLKO. The clock frequencies are coupled to the audio data sampling rate of the input signal by a PLL. The high clock frequencies have to be used if the internal Dolby Digital Bass Management is used. Auxiliary Interface Control bit[11] 0 1 bit[10:7] bit[6] 0 1 bit[5:3] bit[2] 0 1 bit[1] 0 1 bit[0] 0 0 0 All UIC_AUX_ INTERFACE_CTRL Tristate SO* (SOI, SOC, SOD, SOD1..3) enable SO* output tristate SO* output reserved (set to 0) S/PDIF input select select SPDI input select SPDI2 input reserved (set to 0) SO* Impedance low impedance high impedance Serial input select select SID, SII, SIC select SID*, SII*, SIC* reserved Input/output interface selections. 44 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13E0 Function Mode Reset Value (hex) 00000 Name PCM/MPEG De-emphasis Control bit[1:0] 00 MPEG/PCM 01 10 11 De-emphasis automatic detection (only for PCM via S/PDIF and all MPEG-inputs, no deemphasis if PCM via I2S-input is selected) 50/15 s de-emphasis no de-emphasis J17 de-emphasis UIC_DEEMPHASE _CONTROL PCM-signals coming via the serial interface do not contain embedded de-emphasis information. The correct de-emphasis must therefore be initiated by the controller. PCM-signals coming via the S/PDIF-interface and MPEG-data streams contain such information. In this case, the automatic detection should be enabled to achieve the correct de-emphasis. Volume Control D0:13E1 D0:13E2 D0:13E3 D0:13E4 D0:13E5 D0:13E6 D0:13E7 D0:13E8 Volume left channel Volume center channel Volume right channel Volume surround left channel Volume surround right channel Volume subwoofer channel Volume stereo left channel Volume stereo right channel bit[15:8] 7Fhex ... 73hex ... 01hex 00hex +12 dB 0 dB -114 dB mute All 07300 (all) UIC_L_VOLUME UIC_C_VOLUME UIC_R_VOLUME UIC_SL_VOLUME UIC_SR_VOLUME UIC_LFE_ VOLUME UIC_L_ST_ VOLUME UIC_R_ST_ VOLUME The resolution is 1 dB/step. D0:13EA S/PDIF Channel Status Bits Control bit[15] bit[14:8] bit[7:6] bit[5:3] bit[2] bit[1] bit[0] L-bit (generation status) category code should be "0" should be "0" cp-bit (copyright protection) should be "0" for PCM output should be "0" for consumer use All 01904 UIC_CHANNEL _STATUS These bits control the status word in the S/PDIF output. This control is inactive if S/PDIF loop-through is selected. Note: It must be made sure that bits 2, 8, .., 15 are set correctly. Incorrect settings may affect the ability to make digital copies. Micronas Dec. 4, 2003; 6251-598-2PD 45 MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13EE Function Mode PRELIMINARY DATA SHEET Reset Value (hex) 00000 Name Operational Modes (Sec. 2.2 of Pro Logic II LIM Issue 1) Pro Logic II Standard Modes bit[2:0] 000 Dolby Pro Logic II UIC_DPL_ STANDARD Movie Mode Autobalance Surround Filter Surround Coherence (RS Inv.) Panorama Mode Center Width Control Dimension Control Music Mode Autobalance Surround Filter Surround Coherence (RS Inv.) Panorama Mode Center Width Control Dimension Control Virtual compatible Mode Autobalance Surround Filter Surround Coherence (RS Inv.) Panorama Mode Center Width Control Dimension Control Pro Logic Emulation Autobalance Surround Filter Surround Coherence (RS Inv.) Panorama Mode Center Width Control Dimension Control Matrix Mode Autobalance Surround Filter Surround Coherence (RS Inv.) Panorama Mode Center Width Control Dimension Control - (do not use!) Custom Mode Surround Filter Surround Coherence (RS Inv.) Autobalance Panorama Mode Center Width Control Dimension Control Off (Bypass Mode) enabled No enabled disabled disabled neutral (3) 001 disabled Shelf disabled User defined User defined User defined 010 enabled No disabled disabled disabled neutral (3) 011 enabled 7-kHz LP disabled disabled disabled neutral (3) 100 disabled Shelf disabled disabled disabled neutral (3) 101 110 User defined User defined User defined User defined User defined User defined 111 46 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13EE (continued) Function Mode Reset Value (hex) 00000 Name Operational Modes (Sec. 2.2 of Pro Logic II LIM Issue 1) Surround Filter bit[4:3] 00 01 10 No Shelf 7kHz LPF Dolby Pro Logic II UIC_DPL_MODE_ SURR_FILT Surround Coherence bit[5] 0 1 RS Polarity Inversion disabled RS Polarity Inversion enabled UIC_DPL_MODE_ RS_POL Auto-Balance bit[6] 0 1 enabled disabled UIC_DPL_MODE_ AUTO_BAL Panorama Mode bit[7] 0 1 disabled enabled UIC_DPL_MUSIC_ PANORAMA UIC_DPL_MATRIX Pro Logic II Input Matrix bit[9:8] 00 01 10 Stereo or AB Sound A Sound B Dolby Pro Logic II 06060 D0:13ED Music Mode Controls (Sec. 2.1 of Pro Logic II LIM Issue 1) Center Width Control see also "Table 2-2 Center Width Control Levels" of LIM Dolby Pro Logic II UIC_DPL_MUSIC_ CENTER_WIDTH bit[7:5] Control 000 0 001 1 010 2 011 3 (default) 100 4 101 5 110 6 111 7 Angle 00.0 20.8 28.0 36.0 54.0 62.0 69.2 90.0 C Lev.(dB) 0.0 -0.6 -1.1 -1.8 -4.6 -6.6 -9.0 off L/R Lev.(dB) off -12 -9.6 -7.6 -4.8 -4.1 -3.6 -3.0 This control allows center-channel sounds to be positioned between the center speaker and the left/right speakers over a range of eight steps. Step "3" uses a combination of all three front speakers to give the best vocal imaging and most seamless soundstage presentation, and is recommended for most recordings. Step "0" places all center sound in the center speaker. Step "7" places all center sound equally in the left/right speakers, just as in conventional stereo. Micronas Dec. 4, 2003; 6251-598-2PD 47 MAS 35xyH Table 3-7: Configuration memory cells, continued Memory Address (hex) D0:13ED (continued) PRELIMINARY DATA SHEET Function Mode Reset Value (hex) 06060 Name Music Mode Controls (Sec. 2.1 of Pro Logic II LIM Issue 1) Dimension Control bit[15:13] 000 001 010 011 100 101 110 0 1 2 3 (default) 4 5 6 Most Center Dolby Pro Logic II UIC_DPL_MUSIC_ DIMENSION Neutral Most Surround This control allows the user to gradually adjust the sound field either towards the front or the rear. This can be useful to help achieving the desired balance from all the speakers with certain recordings that may contain either too much or too little spatial effect. Step "3" is the recommended setting, which has no effect on the sound. Steps 2, 1, and 0 gradually move the sound forward, and steps 4, 5, and 6 move the sound towards the surrounds. Note: Center Width Control and Dimension Control with higher resolution may be implemented in firmware in a later version of the MAS 35xyH. Therefore, bits[4:0] and bits[12:8] must be set to 0. 48 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 3.6.3. Hybrid User Interface Cells Table 3-8: Hybrid User Interface Cells Memory Address (hex) D0:13FF Function Reset Value (hex) All 00000 Name Message Constants Messages bit[19:0] 0 no error 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 40 41 42 43 44 45 46 47 48 49 50 51 52 53 ... UIH_LAST_ MESSAGE all errors with an error number higher or equal to this error number cause a restart S/PDIF: sync lost during look for Pa, Pb, Pc, Pd S/PDIF: sync lost during operation Data Stream Error (Pa not correct) Data Stream Error (Pb not correct) Data Stream Error (Pc not correct) Data Stream Error (Pd to big) I2S time-out error no input data type selected in I2S input mode (i.e. auto-detection is ON) input type over S/PDIF changed from pcm to data AC-3: initial waiting time out AC-3: sync waiting time out AC-3: sync lost AC-3: header corrupted AC-3: CRC1 wait time-out AC-3: CRC1 fail AC-3: CRC2 wait time-out AC-3: CRC2 fail selected bit-stream-number not available PCM recognition inconsistent, restart DATA TYPE in BurstInfo not AC-3, PCM, MPEG, or DTS. AC-3 - Sampling frequency changed invalid exponents detected S/PDIF: Input type chosen manually (not autodetected) AC3: Input buffer overrun - the input pointer overwrites the actual frame S/PDIF input parity error MPEG: sampling frequency changed MPEG no header found MPEG: no Layer 2 header found MPEG: restart forced MPEG: not enough data to decode MPEG: S/PDIF error MPEG: decoding error MPEG: input time-out MPEG: sync error MPEG: data rate too high (probably PCM input) LM_USER_CHANGE LM_IO_CONTROL LM_NOISE LM_C_DELAY Micronas Dec. 4, 2003; 6251-598-2PD 49 MAS 35xyH Table 3-8: Hybrid User Interface Cells, continued Memory Address (hex) D0:13FF (continued) PRELIMINARY DATA SHEET Function Reset Value (hex) LM_SL_DELAY LM_RL_DELAY LM_OUT_LFE LM_OUT_MODE_CONTROL LM_COMPRESSION_CONTROL LM_CUT_X LM_BOOST_Y LM_POST_PROCESSING LM_SAMP_FREQ LM_OUTN_CHANNELS LM_KARAOKE_MODE LM_DOWNMIX_MODE LM_OUT_CLK_SCALE PCM: Sampling frequency changed in PCM Mode DTS: LOST_SYNC DTS: WRONG_DSYNC DTS: NBLKS_ERROR DTS: FSIZE_ERROR DTS: SFREQ_ERROR DTS: FS_CHANGED DTS: PCMR_ERROR DTS: VERNUM_ERROR DTS: PCHS_ERROR DTS: SUBS_ERROR DTS: VQSUBS_ERROR DTS: JOINX_ERROR DTS: SSC_ERROR DTS: ABITSHuff_ERROR DTS: BLCK_ERROR DTS: AUXCT_ERROR DTS: SCALESHuff_ERROR DTS: AUDIOHuff_ERROR DTS: AUDIOHuff1_ERROR DTS: NOT_VALID_BS; sync found,but not the next one DTS: TIMEOUT_DISCARD DTS: TIMEOUT_FINDSYNC DTS: TIMEOUT_READBYTES DTS: TIMEOUT_SPDIFWAIT1 DTS: TIMEOUT_SPDIFWAIT2 DTS: TIMEOUT_512INPUT DTS: UNSUPPORTED_BS_TYPE; if bs_type=24 or 14 DTS: UNKNOWN_ERROR 00000 Name 54 55 56 57 58 59 60 61 62 63 64 65 66 70 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 UIH_LAST_ MESSAGE The latest message that occurred is displayed in this cell. The controller should frequently (e.g. once per frame) check and clear this memory location. After reading the message it is recommended to clear this cell (by writing a "0") to see whether this message occurs again. 50 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4. Specifications 4.1. Outline Dimensions Fig. 4-1: PMQFP80-11: Plastic Metric Quad Flat Package, 80 leads, 14 x 20 x 2.7 mm3, high standoff Ordering code: QA Weight approximately 1.68 g Micronas Dec. 4, 2003; 6251-598-2PD 51 MAS 35xyH PRELIMINARY DATA SHEET Fig. 4-2: PLCC44-4: Plastic Leaded Chip Carrier, 44 leads, 16.6 x 16.6 x 4.15 mm3, die down, heat slug Ordering code: PR Weight approximately 2.61 g PLCC44-4 is not intended for use in new designs. 52 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = If not used, leave vacant OBL = obligatory, pin must be connected as described in application information VDD: connect to positive supply VSS: connect to ground PLCC44-4 is not intended for use in new designs. Pin No. PMQFP 80-11 PLCC 44-4 Pin Name Type Connection (If not used) Short Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 7 - - 6 5 4 3 - - - 2 - 1 - - - 44 43 42 41 40 - - - 39 AVSS NC NC TE POR I2CC I2CD NC NC NC VDD VDD VSS VSS NC NC SYNC TP TP TP SPDI2 NC NC NC SPREF SUPPLY OBL Ground supply for analog circuits IN IN IN/OUT IN/OUT VSS IN OBL OBL Test enable OBL I2C clock line I2C data line SUPPLY SUPPLY SUPPLY SUPPLY OBL OBL OBL OBL Positive supply for digital parts Positive supply for digital parts Ground supply for digital parts Ground supply for digital parts OUT OUT OUT OUT IN LV LV LV LV LV Reserved for frame synchronization Test pin Test pin Test pin S/PDIF input 2 IN LV S/PDIF input (reference) Micronas Dec. 4, 2003; 6251-598-2PD 53 MAS 35xyH PRELIMINARY DATA SHEET Pin No. PMQFP 80-11 PLCC 44-4 Pin Name Type Connection (If not used) Short Description 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 38 - - - - 37 36 35 34 33 32 31 30 - 29 - - 28 27 26 25 24 - - - - - - - SPDI NC NC NC NC TP TP PI19 PI18 PI17 SIC* (PI16) SII* (PI15) SID* (PI14) NC PI13 NC NC PI12 SOD SOI SOC PI8 NC NC NC NC NC NC XVDD IN LV S/PDIF input 1 LV LV LV IN IN IN (OUT)1) IN (OUT)1) IN (OUT)1) IN (OUT)1) IN (OUT)1) IN (OUT)1) VDD VDD VSS VSS VSS VSS VSS VSS LV IN (OUT)1) VSS LV LV IN (OUT)1) OUT OUT OUT IN (OUT)1) VSS OBL OBL OBL VSS LV LV LV LV LV LV SUPPLY OBL Positive supply for output buffers PIO data [12] Serial output data Serial output frame identification Serial output clock PIO data [8] PIO data [13] Test pin Test pin PIO data [19] PIO data [18] PIO data [17] PIO data[16], SIC* = alternative input for SIC PIO data [15], SII* = alternative input for SII PIO data [14], SID* = alternative input for SID 54 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Pin No. PMQFP 80-11 PLCC 44-4 Pin Name Type Connection (If not used) Short Description 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 - 78 79 80 23 22 - 21 20 19 18 - - - 17 16 15 14 - - - - - - - 13 12 11 10 9 8 XVDD XVSS XVSS SID SII SIC PI4 NC NC NC SPDIFOUT SOD3 SOD2 SOD1 NC NC NC NC NC NC NC CLKO TP NC XTO XTI AVDD SUPPLY SUPPLY SUPPLY IN IN IN IN (OUT)1) OBL OBL OBL VSS VSS VSS VSS LV LV LV Positive supply for output buffers Ground for output buffers Ground for output buffers Serial input data Serial input frame identification Serial input clock PIO data [4] OUT OUT OUT OUT LV LV LV LV LV LV LV LV LV LV LV S/PDIF output Serial output data 3 Serial output data 2 Serial output data 1 OUT OUT LV LV LV DSP clock output Test pin IN/OUT IN SUPPLY OBL LV OBL Quartz oscillator pin 2, input for external clock Quartz oscillator pin 1 Supply for analog circuits Micronas Dec. 4, 2003; 6251-598-2PD 55 MAS 35xyH 4.3. Pin Descriptions 4.3.1. Power Supply Pins Connection of all power supply pins is mandatory for the functioning of the MAS 35xyH. VDD SUPPLY VSS SUPPLY The VDD/VSS pair is internally connected with all digital modules of the MAS 35xyH. XVDD SUPPLY XVSS SUPPLY The XVDD/XVSS pins are internally connected with the pin output buffers. AVDD SUPPLY AVSS SUPPLY The AVDD/AVSS pair is connected internally with the analog blocks of the MAS 35xyH, i.e. clock synthesizer and supply voltage supervision circuits. PRELIMINARY DATA SHEET 4.3.5. Serial Input Interface SID IN SII IN SIC IN Data, frame indication, and clock line of the standard I2S (word mode) serial input interface. PI16 SIC* IN PI15 SII* IN PI14 SID* IN The SIC*, SID*, and SII* are alternative serial input lines. This interface can be selected in memory cell D0:13D0. 4.3.6. S/PDIF Input Interface SPDI IN SPDI2 IN SPREF IN Input lines (SPDI/SPDI2) and ground reference line (SPREF) of the S/PDIF-input interfaces. One of the two alternate input lines is selected by in D0:13DF. 4.3.2. Control Lines I2CC SCL I2CD SDA Standard I2C control lines. IN/OUT IN/OUT 4.3.7. S/PDIF Output Interface SPDIFOUT S/PDIF-output line. OUT 4.3.3. General Purpose Input/Output 4.3.8. Serial Output Interface PI4, PI8, PI12...PI19 IN/OUT General purpose input/output pins. PI14 to PI16 can be used as alternative I2S bus inputs. Function is controlled by the registers PIO_Config, PIO_Direction, PIO_Data_Out, PIO_Data_In. SOD OUT SOD1 OUT SOD2 OUT SOD3 OUT SOI OUT SOC OUT Data, frame indication, and clock line of the serial output interface. The SOI indicates whether the left or the right audio sample is transmitted. Besides the two modes, it is possible to reconfigure the interface. 4.3.4. Clocking XTO IN This is the clock input of the MAS 35xyH. The nominal clock frequency is 18.432 MHz. XTI IN This connection is needed for the quartz oscillator. CLKO OUT The CLKO is an oversampling clock that is synchronized to the digital audio data (SOD) and the frame identification (SOI). 4.3.9. Miscellaneous POR IN The POR pin is used to reset the digital parts of the MAS 35xyH. POR is a low active signal. TE IN The TE pin is for production test only and must be connected with VSS in all applications. SYNC The SYNC pin is set while decoding Dolby Digital or MPEG. Only during header processing, there is a short Low period (20...300 s depending on the audio format) 56 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.4. Pin Configurations NC XVDD XVDD XVSS XVSS SID SII SIC PI4 NC NC NC NC NC NC NC NC PI8 SOC SOI SOD PI12 NC NC SPDIFOUT SOD3 SOD2 SOD1 NC NC NC NC NC NC NC CLKO TP XTO XTI AVDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34 PI13 NC SID* SII* SIC* PI17 PI18 PI19 TP TP NC NC NC NC SPDI SPREF MAS 35xyH 33 32 31 30 29 28 27 26 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AVSS NC NC TE POR I2CC I2CD NC NC NC VDD VDD NC VSS VSS NC TP SYNC TP TP NC SPDI2 NC NC Fig. 4-3: PMQFP80-11 package Micronas Dec. 4, 2003; 6251-598-2PD 57 MAS 35xyH PRELIMINARY DATA SHEET VSS VDD I2CD I2CC POR TE SYNC TP TP TP SPDI2 6 AVSS AVDD XTI XTO N.C. TP CLKO SOD1 SOD2 SOD3 SPDIFOUT 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 SPREF SPDI TP TP PI19 PI18 PI17 PI16 PI15 PI14 PI13 MAS 35xyH 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 PI4 SIC SII SID XVSS XVDD PI8 SOI SOC PI12 SOD Fig. 4-4: PLCC44-4 package PLCC44-4 is not intended for use in new designs. 58 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.5. Internal Pin Circuits VDD TTLIN P N Fig. 4-5: Input pins PCS, PR VSS Fig. 4-10: Input/Output pins SIC, SII, SID Fig. 4-6: Input pin TE VDD N VSS Fig. 4-7: Input pin POR Fig. 4-11: Input/Output pins I2CC, I2CD AVDD P VDD P XTI P P N N N XTO VSS Fig. 4-12: Output pins CLKO,SYNC N Enable AVSS VDD Fig. 4-8: Clock oscillator XTI, XTO SPDI, SPDI2 SPREF VDD P Bias Fig. 4-13: S/PDIF Input N VSS Fig. 4-9: Input/Output pins SOD1, SOD2, SOD3, SPDIFOUT, PI4, PI8, SOC, SOI, SOD, PI12...PI19 VDD - + Micronas Dec. 4, 2003; 6251-598-2PD 59 MAS 35xyH 4.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip PRELIMINARY DATA SHEET 4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (0 V, VSS) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. PLCC44-4 is not intended for use in new designs. Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min. TA1) Ambient Operating Temperature PMQFP80-11 PLCC44-4 Case Operating Temperature PMQFP80-11 PLCC44-4 Storage Temperature Power Dissipation PMQFP80-11 PLCC44-4 Supply Voltage Voltage differences within supply domains Input Voltage Input Current Output Voltage Output Current all digital pins all digital pins all digital pins all digital pins - 0 0 - 0 0 - VDD, XVDD, AVDD -0.3 -0.5 -0.3 -20 -0.3 -40 105 105 125 1550 1250 6.0 0.5 VSUP +0.3 20 VSUP +0.3 250 C mW mW V V V mA V mA Limit Values Max. 652) 65 C Unit TC C TS PMAX VSUP VSUP VI II VO IO 1) Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power consumption allowed for this package A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the "Absolute Maximum Ratings" must not be exceeded at worst case conditions of the application. 2) 60 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.6.2. Recommended Operating Conditions (TA = 0 to +65 C) Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (0 V, VSS) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep VDD = AVDD = XVDD during all power-up and power-down sequences. PLCC44-4 is not intended for use in new designs. 4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min. TA Ambient Operating Temperature PMQFP80-11 PLCC44-4 Case Operating Temperature PMQFP80-11 PLCC44-4 Power Dissipation PMQFP80-11 PLCC44-4 Supply Voltage Input Voltage Low3) Input Voltage High3) Input Voltage Low (digital)3) Input Voltage High (digital)3) - 0 - 0 VDD, XVDD, AVDD VDD, XVDD, AVDD POR I2CC, I2CD PI, SII, SIC, SID, PR, TE, 4.75 5.0 105 105 15502) 12502) 5.25 0.5 2.6 0.5 VSUPD 0.5 mW mW V V V V Limit Values Typ. - Max. 651) 65 C Unit TC C PMAX VSUP VIL VIH VILD VIHD 1) A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the "Recommended Operating Conditions" must not be exceeded at worst case conditions of the application. PMAX variation: user-determined by application circuit for I/Os Input levels at VDD = 4.5 V...5.5 V 2) 3) Micronas Dec. 4, 2003; 6251-598-2PD 61 MAS 35xyH 4.6.2.2. Reference Frequency Generation and Crystal Recommendations Symbol Parameter Pin Name Min. External Clock Input Recommendations CLKF CLKAmp Clock frequency Clock amplitude XTO 0.7 PRELIMINARY DATA SHEET Limit Values Typ. Max. Unit 18.432 3.5 MHz Vpp Crystal Recommendations TAC fP f/fS f/fS REQ C0 Ambient temperature range Load resonance frequency at CI = 12 pF Accuracy of frequency adjustment Frequency variation vs. temperature Equivalent series resistance Shunt (parallel) capacitance -50 -50 12 3 XTI, XTO -20 18.432 50 50 30 7 80 C MHz ppm ppm pF 4.6.3. Characteristics at TA = 0 to 65 C, VDD = 5.0 V, fCrystal = 18.432 MHz 4.6.3.1. General Characteristics Symbol Parameter Pin Name Min. Supply Current ISUP Current consumption all supply pins 210 mA 5.0 V, audio sampling frequency 48 kHz Dolby Digital, 61 MHz fproc Limit Values Typ. Max. Unit Test Conditions Digital Outputs and Inputs ODigL ODigH Output low voltage Output high voltage PI, SOI, SOC, SOD, SOD1, SOD2, SOD3, EOD, RTR, RTW, CLKO SPDIF-OUT all digital Inputs 0.5 VSUP -0.5 V V at Iload = 1 mA at Iload = 1 mA CDigI IDLeak Input capacitance Input leakage current 7 -1 1 pF A 0 V < Vpin < VSUP 62 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.6.3.2. I2C Characteristics Symbol Parameter Pin Name Min. RON fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 Output resistance I2C bus frequency I2C START condition setup time I2C STOP condition setup time I2C clock low pulse time I2C clock high pulse time I2C data hold time before rising edge of clock I2C data hold time after falling edge of clock I2C output low voltage I2C output high leakage current I2C data output hold time after falling edge of clock I2C data output setup time before rising edge of clock I2CC, I2CD I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD 20 250 300 300 1250 1250 80 80 0.3 1 Limit Values Typ. Max. 60 400 kHz ns ns ns ns ns ns V A ns ns fI2C = 400kHz ILOAD = 5 mA VI2CH = 5.5 V Iload = 5 mA, VDD = 4.5 V Unit Test Conditions 1/fI2C tI2C4 H L tI2C3 I2CC tI2C1 tI2C5 tI2C6 tI2C2 H L I2CD as input tI2COL2 tIC2OL1 H L I2CD as output Fig. 4-14: I2C timing diagram Micronas Dec. 4, 2003; 6251-598-2PD 63 MAS 35xyH 4.6.3.3. S/PDIF Bus Input Characteristics Symbol Parameter Pin Name Min. VS fs1 fs2 fs3 tp tr tf Signal amplitude Biphase frequency Biphase frequency Biphase frequency Biphase period Rise time Fall time Duty-cycle SPDI, SPDI2, SPDI, SPDI2 SPDI, SPDI2 SPDI, SPDI2 SPDI, SPDI2 SPDI, SPDI2 SPDI, SPDI2 SPDI, SPDI2 0 0 40 50 200 Limit Values Typ. 500 3.072 2.822 2.048 326 65 65 60 Max. 1000 PRELIMINARY DATA SHEET Unit Test Conditions mVpp MHz MHz MHz ns ns ns % 1000 ppm, fs = 48 kHz 1000 ppm, fs = 44.1 kHz 1000 ppm, fs = 32 kHz at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at fs = 48 kHz, (highest sampling rate) at "1" and fs = 48 kHz tf tr 90% 10% 90% 10% tp Fig. 4-15: Timing of the S/PDIF-input VS 64 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.6.3.4. S/PDIF Bus Output Characteristics Symbol Parameter Pin Name Min. fs1 fs2 fs3 tp tr tf Biphase frequency Biphase frequency Biphase frequency Biphase period Rise time Fall time Duty-cycle SPDIFOUT SPDIFOUT SPDIFOUT SPDIFOUT SPDIFOUT SPDIFOUT SPDIFOUT 0 0 50 Limit Values Typ. 3.072 2.822 2.048 326 2 2 Max. MHz MHz MHz ns ns ns % fs = 48 kHz fs = 44.1 kHz fs = 32 kHz at fs = 48 kHz, (highest sampling rate) Cload = 10 pF Cload = 10 pF at "1" and fs = 48 kHz Unit Test Conditions tf tr 90% 10% 90% 10% tp Fig. 4-16: Timing of the S/PDIF output VS Micronas Dec. 4, 2003; 6251-598-2PD 65 MAS 35xyH 4.6.3.5. I2S Bus Characteristics - Input Symbol Parameter Pin Name Min. tSICLK tSIDDS tSIDDH tSIIDS I2S clock input clock period I2S data setup time before falling edge of clock I2S data hold time I2S word strobe setup time before falling(/rising) edge of clock I2S word strobe hold time Burst wait time SIC SIC, SID SIC, SID SIC, SII 960 50 50 50 tSICLK -100 tSICLK -100 Limit Values Typ. Max. PRELIMINARY DATA SHEET Unit Test Conditions ns ns ns ns Burst mode, mean data rate < 150 kbit/s tSIIDH tbw SIC, SII SIC, SID 50 480 ns ns TSICLK H SIC L H (SII) L H SID L TSIDDS TSIDDH Fig. 4-17: Serial input of continuous data stream (SII must be held down). Data values are latched with falling clock per default. Vh SIC Vl ... data valid at falling edge of clock ... Vh SID Vl 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 Vh SIII2S Vl left 32-bit audio sample right 32-bit audio sample Fig. 4-18: Serial input of I2S signal (PCM). Data values are latched with rising clock per default. 66 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 4.6.3.6. I2S Characteristics - Output Symbol Parameter Pin Name Min. tSCLKO tSOISS tSOODC I2S clock output frequency I2S word strobe hold time after falling edge of clock I2S data hold time after falling edge of clock SOC SOC, SOI SOC, SOD 10 10 Limit Values Typ. 325 tSCLK O/2 tSCLK O/2 Max. ns ns ns 48 kHz sample rate 2x32 bits/sample Unit Test Conditions TSCLKO H SOC L H SOI L TSOISS H TSOISS SOD L TSOODC Fig. 4-19: I2S-output. Data values are valid with rising clock per default. Vh SOC Vl ... ... Vh SOD Vl 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 Vh SOI Vl left 32-bit audio sample right 32-bit audio sample Fig. 4-20: Schematic timing of the SDO interface in 32 bit/sample mode Micronas Dec. 4, 2003; 6251-598-2PD 67 MAS 35xyH PRELIMINARY DATA SHEET Detail A 0 19 20 Detail B 31 32 51 52 63 64 SCLOCK SSYNC SDATA MSB LSB (20-bit) Aux Data "A" MSB LSB (20-bit) Aux Data "B" MSB Subframe 1 (left) Audio Data Subframe 1 (right) Audio Data Subframe 1 Fig. 4-21: Serial interface format for multichannel mode. 4.6.4. Firmware Characteristics Symbol Parameter Pin Name Min. Synchronization Times for Dolby Digital Mode tDDsync Synchronization on Dolby Digital Bit Streams 140 ms fs = 48 kHz, AC-3 Limit Values Typ. Max. Unit Test Conditions Synchronization Times for MPEG-Mode tmpgsync Ranges PLLRange Tracking range of sampling clock recovery PLL -200 200 ppm Synchronization on MPEG Bit Streams 120 48 ms fs = 48 kHz, MPEG 68 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH 5. Application CTRL 47 +5VD SPDIF NC 47 SPDIF IC1 MAS 35xyH SPDO SPDIF out PI16 PI15 PI14 PI14 47 10/16V +5VD 100n 10/16V 47 +5VD 1n Surround R 1n Surround L Center 1n 1n 4 1n 1n 22 22 22 22 IC2 TP DPL 4519G NC NC NC 10/16V +8V 100H 10/16V 33/16V 330n 330n 330n 330n 330n 330n 47 10/16V +5VA Fig. 5-1: Part 1 of the application circuit diagram. For details please refer to the Micronas Digital Multichannel Audio application kit Micronas Dec. 4, 2003; 6251-598-2PD 69 MAS 35xyH PRELIMINARY DATA SHEET Fig. 5-2: Part 2 of the application diagram. For details please refer to the Micronas Digital Multichannel Audio application kit. 4 70 Dec. 4, 2003; 6251-598-2PD Micronas PRELIMINARY DATA SHEET MAS 35xyH Micronas Dec. 4, 2003; 6251-598-2PD 71 MAS 35xyH 6. Data Sheet History 1. Preliminary Data Sheet: "MAS 3529H Audio Decoder IC Family", Sept. 24, 2002, 6251-598-1PD. First release of the preliminary data sheet. 2. Preliminary Data Sheet: "MAS 35xyH Audio Decoder IC Family", Dec. 4, 2003, 6251-598-2PD. Second release of the preliminary data sheet. Major changes: - Specification for PMQFP80-11 package added. - New package diagram for PLCC44-4 PRELIMINARY DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-598-2PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 72 Dec. 4, 2003; 6251-598-2PD Micronas |
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